IDT723631 データシートの表示（PDF） - Integrated Device Technology
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IDT723631 Datasheet PDF : 23 Pages
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IDT723631/723641/723651 CMOS SyncFIFO™
512 x 36, 1024 x 36, 2048 x 36
CLKA
4
COMMERCIAL TEMPERATURE RANGE
RST
IR
FS1/SEN
tFSS
tFSS
tSPH
tFSH
tSENS
tSDS
tSENH
tSDH
tPIR
tSENS
tSENH
tSDS
tSDH
FS0/SD
AF Offset
(Y) MSB
AE Offset
(X) LSB
NOTE:
1. It is not necessary to program offset register bits on consecutive clock cycles. FIFO write attempts are ignored until IR is set HIGH.
Figure 3. Programming the Almost-Full Flag and Almost-Empty Flag Offset Values Serially
3023 drw 06
CLKA
t CLKH
tCLK
tCLKL
IR HIGH
CSA
W/RA
MBA
ENA
A0 - A35
tENS2
tENS2
tENH2
tENH2
tENS2
tENH2
tENS1
tENH1
tDS
tDH
W1
tENS1
tENH1
W2
CLKB
tCLKH
tCLK
t CLKL
Figure 4. FIFO Write-Cycle Timing
OR HIGH
CSB
W/RB
MBB
ENB
B0 - B35
tENS1
t ENH1
t ENS1
tENH1
tMDV
tEN
tA
W1
tA
W2
Figure 5. FIFO Read-Cycle Timing
t ENS1
t ENH1
No Operation
3023 drw 07
tENS1
tENH1
No
Operation
W3
tDIS
3023 drw 08
14
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