NM24C04UFN データシートの表示（PDF） - Fairchild Semiconductor

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NM24C04UFN

4K-Bit Serial EEPROM 2-Wire Bus Interface

Fairchild Semiconductor 

Write Cycle Timing (Figure 1)

SCL

SDA

8th BIT ACK

Note:

WORD n

tWR

STOP

START

CONDITION

CONDITION

The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle.

Data Validity (Figure 2)

DS800008-10

SDA

SCL

DATA STABLE DATA

CHANGE

Start and Stop Definition (Figure 3)

SDA

SCL

START

CONDITION

Acknowledge Response from Receiver (Figure 4)

SCL FROM

MASTER

DATA OUTPUT

FROM

TRANSMITTER

DATA OUTPUT

FROM

RECEIVER

1

START

DS800008-11

STOP

CONDITION

DS800008-12

8

9

ACKNOWLEDGE

DS800008-13

8

NM24C04U/NM24C05U Rev. C.1

www.fairchildsemi.com

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