ISL6444 データシートの表示（PDF） - Intersil

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ISL6444

Dual PWM Controller with DDR Memory Option for Gateway Applications

Intersil 

Block Diagram

BOOT1

UGATE1

PHASE1

UG1

HI

OVP1

LGATE1

PGND1

GATE

CONTROL

VCC

LG1

OVP1

GATE LOGIC

LO

MODE CHANGE COMP 1

-

HYST COMP 1

-

SOFT1 EN1 EN2 SOFT2

REFERENCE

AND

SOFT START

SDWN1

SDWN2

REF=0.9V

UG2

HI

OVP2

GATE LOGIC

LO

GATE

CONTROL

VCC

LG2

OVP2

MODE CHANGE COMP 2

-

HYST COMP 2

-

BOOT2

UGATE2

PHASE2

LGATE2

PGND2

VSEN1

VREF

ISEN1

EA1

--

Σ

-

LGATE1

LGATE1

- CSA1

OC COMP1

-

OC LOGIC1

-

Σ

EA2

--

OC COMP2

OC LOGIC2

-

LGATE2

CSA2

-

S2e

LGATE2

VCC

GND

VSEN1 OVP1

OUTPUT

VOLTAGE

MONITOR

PG1

OCSET1

1.24V

RAMP 1

ϕ=90o

S1

S2a

ϕ=0o CLK ϕ=180o

RAMP 2

S2b

VCC

VIN

1.24V

S2c

OVP2 VSEN2

OUTPUT

VOLTAGE

MONITOR

-

S2d

OCSET2

PG2/REF

VSEN2

ISEN2

DDR

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