ISL6554 データシートの表示（PDF） - Intersil

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ISL6554

Microprocessor CORE Voltage Regulator Using Multi-Phase Buck PWM Control Without Programmable Droop

Intersil 

Block Diagram

ISL6554

PGOOD

VCC

VSEN

COMP

VID4

VID3

VID2

VID1

VID0

FB

X 0.9

X1.15

UV

+

-

OVP

+

-

OV

LATCH

S

POWER-ON

RESET (POR)

CLOCK AND

SAWTOOTH

GENERATOR

THREE

STATE

+

∑

-

PWM

+

-

SOFT-

START

AND FAULT

LOGIC

+∑

-

PWM

+

-

+

∑

-

PWM

+

-

D/A

+ E/A

-

+

∑

-

PWM

+

-

CURRENT

CORRECTION

I_TOT

+

+

+

∑+

-

+

OC I_TRIP

PHASE

NUMBER CHANNEL

DETECTOR

GND

FS/EN

PWM1

PWM2

PWM3

PWM4

ISEN1

ISEN2

ISEN3

ISEN4

2

FN9003.3

February 11, 2005

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