ISL84521, ISL84522, ISL84523
Test Circuits and Waveforms (Continued)
V+
C
SWITCH
OUTPUT
VOUT
LOGIC ON
INPUT
∆VOUT
OFF
Q = ∆VOUT x CL
3V
ON
0V
RG
NO OR NC
COM
VG
GND IN
C
V-
LOGIC
INPUT
VOUT
CL
Logic input waveform is inverted for switches that have the opposite
logic sense.
FIGURE 2A. MEASUREMENT POINTS
Repeat test for all switches. CL includes fixture and stray
capacitance.
FIGURE 2B. TEST CIRCUIT
FIGURE 2. CHARGE INJECTION
V+
C
3V
LOGIC
INPUT
0V
SWITCH
OUTPUT
VOUT1 0V
SWITCH
OUTPUT
VOUT2 0V
90%
90%
tD
90%
90%
tD
C
VNX
LOGIC
INPUT
NO1
NC2
IN1
IN2
COM1
COM2
VOUT1
VOUT2 RL1
300Ω
CL1
35pF
RL2
300Ω
CL2
35pF
GND
C
V-
CL includes fixture and stray capacitance.
Reconfigure accordingly to test SW3 and SW4.
FIGURE 3A. MEASUREMENT POINTS
FIGURE 3B. TEST CIRCUIT
FIGURE 3. BREAK-BEFORE-MAKE TIME (ISL84523 ONLY)
SIGNAL
GENERATOR
V+
C
NO OR NC
IN 0V OR 2.4V
ANALYZER
RL
COM
GND
Repeat test for all switches.
C
V-
FIGURE 4. OFF ISOLATION TEST CIRCUIT
6
RON = V1/1mA
VNX
NO OR NC
1mA
V1
V+
C
IN
0.8V OR 2.4V
COM
GND
Repeat test for all switches.
C
V-
FIGURE 5. RON TEST CIRCUIT