ISL90842UIV1427(2005) データシートの表示（PDF） - Intersil

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ISL90842UIV1427
(Rev.:2005)

Quad Digital Controlled Potentiometers (XDCP™)

Intersil 

Block Diagram

ISL90842

VCC

WR3

SDA

SCL

I2C

INTERFACE

POWER-UP,

INTERFACE,

CONTROL AND

STATUS LOGIC

WR2

WR1

A1

WR0

A0

DCP3

RH3

X * RW3

DCP2

RH2

X * RW2

DCP1

RH1

X * RW1

DCP0

RH0

X * RW0

WP

GND

*The RL pins of each potentiometer are left floating

Pin Descriptions

TSSOP PIN

1

2

3

4

5

6

7

8

9

10

11

12

13

14

SYMBOL

RH3

RW3

SCL

SDA

GND

RW2

RH2

RW1

RH1

A0

A1

VCC

RH0

RW0

DESCRIPTION

“High” terminal of DCP3

“Wiper” terminal of DCP3

I2C interface clock

Serial data I/O for the I2C interface

Device ground pin

“Wiper” terminal of DCP2

“High” terminal of DCP2

“Wiper” terminal of DCP1

“High” terminal of DCP1

Device address for the I2C interface

Device address for the I2C interface

Power supply pin

“High” terminal of DCP0

“Wiper” terminal of DCP0

2

FN8096.0

June 14, 2005

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