ISL90842(2005) データシートの表示（PDF） - Intersil
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ISL90842 Datasheet PDF : 12 Pages
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ISL90842
Operating Specifications Over the recommended operating conditions unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
ICC1
VCC supply current
(Volatile write/read)
fSCL = 400kHz; SDA = Open; (for I2C, Active, Read and
Write States)
ISB
VCC current (standby)
VCC = +5.5V, I2C Interface in Standby State
VCC = +3.6V, I2C Interface in Standby State
ILkgDig Leakage current, at pins A0, Voltage at pin from GND to VCC
A1, SDA and SCL pins
TYP
MIN (NOTE 1) MAX
1
UNITS
mA
5
µA
2
µA
-10
10
µA
tDCP DCP wiper response time
(Note 15)
SCL falling edge of last bit of DCP Data Byte to wiper
change
1
µs
Vpor Power-on recall voltage
Minimum VCC at which memory recall occurs
1.8
VccRamp VCC ramp rate
0.2
tD (Note 15) Power-up delay
VCC above
completed,
Vpor, to
and I2C
DCP Initial
Interface in
Value Register
standby state
recall
2.6
V
V/ms
3
ms
SERIAL INTERFACE SPECS
VIL
A1, A0, SDA, and SCL input
buffer LOW voltage
-0.3
0.3*VCC V
VIH A1, A0, SDA, and SCL input
buffer HIGH voltage
0.7*VCC
VCC+0.3 V
Hysteresis SDA and SCL input buffer
(Note 15) hysteresis
VOL SDA output buffer LOW
(Note 15) voltage, sinking 4mA
0.05*
VCC
0
V
0.4
V
Cpin A1, A0, SDA, and SCL pin
(Note 15) capacitance
10
pF
fSCL SCL frequency
tIN
Pulse width suppression time Any pulse narrower than the max spec is suppressed.
(Note 15) at SDA and SCL inputs
400
kHz
50
ns
tAA SCL falling edge to SDA
(Note 15) output data valid
tBUF Time the bus must be free
(Note 15) before the start of a new
transmission
SCL falling edge crossing 30% of VCC, until SDA exits the
30% to 70% of VCC window.
SDA crossing 70% of VCC during a STOP condition, to SDA
crossing 70% of VCC during the following START condition.
1300
900
ns
ns
tLOW Clock LOW time
Measured at the 30% of VCC crossing.
1300
ns
tHIGH Clock HIGH time
Measured at the 70% of VCC crossing.
600
ns
tSU:STA START condition setup time SCL rising edge to SDA falling edge. Both crossing 70% of 600
ns
VCC.
tHD:STA START condition hold time From SDA falling edge crossing 30% of VCC to SCL falling 600
ns
edge crossing 70% of VCC.
tSU:DAT Input data setup time
From SDA exiting the 30% to 70% of VCC window, to SCL 100
ns
rising edge crossing 30% of VCC
tHD:DAT Input data hold time
From SCL rising edge crossing 70% of VCC to SDA entering 0
ns
the 30% to 70% of VCC window.
tSU:STO STOP condition hold time
From SCL rising edge crossing 70% of VCC, to SDA rising 600
ns
edge crossing 30% of VCC.
4
FN8096.0
June 14, 2005
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