5811W データシートの表示（PDF） - Intersil
部品番号
コンポーネント説明
メーカー
5811W Datasheet PDF : 14 Pages
| |||
ISL95811
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
(Note 18) (Note 4) (Note 18) UNITS
fSCL
tIN
SCL Frequency
Pulse Width Suppression Time at
SDA and SCL Inputs
Any pulse narrower than the max spec is
suppressed.
400 kHz
50
ns
tAA
tBUF
SCL Falling Edge to SDA Output
Data Valid
Time the Bus Must be Free Before
the Start of a New Transmission
SCL falling edge crossing 30% of VCC, until
SDA exits the 30% to 70% of VCC window.
SDA crossing 70% of VCC during a STOP
condition, to SDA crossing 70% of VCC during
the following START condition.
1300
900
ns
ns
tLOW
Clock LOW Time
Measured at the 30% of VCC crossing.
1300
ns
tHIGH
Clock HIGH Time
Measured at the 70% of VCC crossing.
600
ns
tSU:STA
START Condition Setup Time
SCL rising edge to SDA falling edge. Both
600
ns
crossing 70% of VCC.
tHD:STA
START Condition Hold Time
From SDA falling edge crossing 30% of VCC to 600
ns
SCL falling edge crossing 70% of VCC.
tSU:DAT
Input Data Setup Time
From SDA exiting the 30% to 70% of VCC
100
ns
window, to SCL rising edge crossing 30% of
VCC
tHD:DAT
Input Data Hold Time
From SCL rising edge crossing 70% of VCC to
0
ns
SDA entering the 30% to 70% of VCC window.
tSU:STO
STOP Condition Setup Time
From SCL rising edge crossing 70% of VCC, to 600
ns
SDA rising edge crossing 30% of VCC.
tHD:STO
STOP Condition Hold Time for Read, From SDA rising edge to SCL falling edge. Both 600
ns
or Volatile Only Write
crossing 70% of VCC.
tHD:STO:NV STOP Condition Hold Time for Non- From SDA rising edge to SCL falling edge. Both
2
µs
Volatile Write
crossing 70% of VCC.
tDH
Output Data Hold Time
From SCL falling edge crossing 30% of VCC,
0
ns
until SDA enters the 30% to 70% of VCC
window.
tR (Note 16) SDA and SCL Rise Time
From 30% to 70% of VCC
20 +
0.1 * Cb
250
ns
tF (Note 16) SDA and SCL Fall Time
From 70% to 30% of VCC
20 +
0.1 * Cb
250
ns
Cb (Note 16) Capacitive Loading of SDA or SCL Total on-chip and off-chip
10
400
pF
Rpu (Note 16) SDA and SCL Bus Pull-Up Resistor Maximum is determined by tR and tF.
1
kΩ
Off-Chip
For Cb = 400pF, max is about 2kΩ~2.5kΩ.
For Cb = 40pF, max is about 15kΩ~20kΩ
tWC (Note 17) Non-Volatile Write Cycle Time
12
20
ms
tSU:WP
WP Setup Time
Before START condition
600
ns
tHD:WP
WP Hold Time
After STOP condition
600
ns
NOTES:
4. Typical values are for TA = +25°C and 3.3V supply voltage.
5. LSB: [V(RW)255 – V(RW)0]/255. V(RW)255 and V(RW)0 are V(RW) for the DCP register set to FF hex and 00 hex respectively. LSB is the
incremental voltage when changing from one tap to an adjacent tap.
6. ZS error = V(RW)0/LSB.
7. FS error = [V(RW)255 – VCC]/LSB.
8. DNL = [V(RW)i – V(RW)i-1]/LSB-1, for i = 1 to 255. i is the DCP register setting.
5
FN6759.1
October 6, 2008
Share Link: 