ISL97671AIRZ-EVALZ データシートの表示（PDF） - Intersil
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ISL97671AIRZ-EVALZ Datasheet PDF : 28 Pages
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ISL97671A
Output Channel Mask/Fault Readout
Register (0x09)
This register can be read or write; the bit position corresponds to
the channel. For example, Bit 0 corresponds to Ch0 and bit
5corresponds to Ch5 and so on. Writing data to this register, it
enables the channels of interest. When reading data from this
register, any disabled channel and any faulted out channel will
read as 0. This allows the user to determine which channel is
faulty and optionally not enabling it in order to allow the rest of
the system to continue to function. Additionally, a faulted out
channel can be disabled and re-enabled in order to allow a retry
for any faulty channel without having to power-down the other
channels.
The bit assignment is shown in Figure 36. The default for
Register 0x09 is 0x3F.
REGISTER 0x08
CONFIGURATION REGISTER
RESERVED
Bit 7 (R/W)
RESERVED
Bit 6 (R/W)
BIT5
0 (W)
BIT4
1(W)
BIT3
1(W)
FSW
Bit 2 (R/W)
RESERVED
Bit 1 (R/W)
VSC
Bit 0 (R/W)
BIT ASSIGNMENT
DirectPWM
BITS[5-3]
FSW
VSC[0]
BIT FIELD DEFINITIONS
Forces the PWMI signal to directly control the current sources. Note that
there is some synchronous delay between PWMI and current sources.
These bits should always be written as 011
2 levels of Switching Frequencies (1 = 1,200kHz, 0 = 600kHz)
2 levels of Short-Circuit Thresholds (0 = disabled, 1 = 7.5V minimum)
FIGURE 35. DESCRIPTIONS OF CONFIGURATION REGISTER
REGISTER 0x09
OUTPUT CHANNEL REGISTER
RESERVED
Bit 7 (R/W)
RESERVED
Bit 6 (R/W)
CH5
Bit 5 (R/W)
CH4
Bit 4 (R/W)
CH3
Bit 3 (R/W)
CH2
Bit 2 (R/W)
CH1
Bit 1 (R/W)
CH0
Bit 0 (R/W)
BIT ASSIGNMENT
CH[5..0]
BIT FIELD DEFINITIONS
CH5 = Channel 5, CH4 = Channel 4 and so on
FIGURE 36. OUTPUT CHANNEL REGISTER
23
FN7709.1
March 24, 2011
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