ISL97671AIRZ-EVALZ データシートの表示（PDF） - Intersil

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ISL97671AIRZ-EVALZ

6-Channel SMBus/I2C or PWM Dimming LED Driver with Phase Shift Control

Intersil 

ISL97671A

REGISTER 0x0A

PHASE SHIFT CONTROL REGISTER

EQUALPHASE

Bit 7 (R/W)

PHASESHIFT6

Bit 6 (R/W)

PHASESHIFT5

Bit 5 (R/W)

PHASESHIFT4

Bit 4 (R/W)

PHASESHIFT3

Bit 3 (R/W)

PHASESHIFT2

Bit 2 (R/W)

PHASESHIFT1

Bit 1 (R/W)

PHASESHIFT0

Bit 0 (R/W)

BIT ASSIGNMENT

EqualPhase

PhaseShift[6..0]

BIT FIELD DEFINITIONS

Controls phase shift mode - When 0, phase shift is defined by PhaseShift<6:0>. When 1, phase shift

is 360/N (where N is the number of channels enabled).

7-bit Phase shift setting - phase shift between each channel is PhaseShift<6:0>/(255*PWMFreq)

In direct PWM modes, phase shift between each channel is PhaseShift<6:0>/12.8MHz

FIGURE 37. DESCRIPTIONS OF PHASE SHIFT CONTROL REGISTER

Phase Shift Control Register (0x0A)

The Phase Shift Control register is used to set phase delay

between each channels. When bit 7 is set high, the phase delay

is set by the number of channels enabled and the PWM

frequency. Refer to Figures 3 and 4, the delay time is defined by

Equation 17:

tD1 = (tFPWM ⁄ N)

(EQ. 17)

where N is the number of channels enabled, and tFPWM is the

period of the PWM cycle. When bit 7 is set low, the phase delay is

set by bits 6 to 0 and the PWM frequency. Referencing Figure 24,

the programmable delay time is defined by Equation 18:

tPD = (PS < 6, 0 > xtFPWM ⁄ (255))

(EQ. 18)

where PS is an integer from 0 to 127, and tFPWM is the period of

the PWM cycle. By default, all the register bits are set low, which

sets zero delay between each channel. Note that the user should

not program the register to give more than one period of the

PWM cycle delay between the first and last enabled channels.

Components Selections

According to the inductor Voltage-Second Balance principle, the

change of inductor current during the switching regulator On

time is equal to the change of inductor current during the

switching regulator Off time. Since the voltage across an inductor

is:

VL = L × ΔIL ⁄ Δt

(EQ. 19)

and ΔIL at On = ΔIL at Off, therefore:

(VI – 0 ) ⁄ L × D × tS= (VO – VD – VI) ⁄ L × (1 – D ) × tS

(EQ. 20)

where D is the switching duty cycle defined by the turn-on time

over the switching period. VD is Schottky diode forward voltage

that can be neglected for approximation.

Rearranging the terms without accounting for VD gives the boost

ratio and duty cycle respectively as:

VO ⁄ VI = 1 ⁄ (1 – D)

(EQ. 21)

D = (VO – VI ) ⁄ VO

(EQ. 22)

Input Capacitor

Switching regulators require input capacitors to deliver peak

charging current and to reduce the impedance of the input

supply. This reduces interaction between the regulator and input

supply, thereby improving system stability. The high switching

frequency of the loop causes almost all ripple current to flow in

the input capacitor, which must be rated accordingly.

A capacitor with low internal series resistance should be chosen

to minimize heating effects and improve system efficiency, such

as X5R or X7R ceramic capacitors, which offer small size and a

lower value of temperature and voltage coefficient compared to

other ceramic capacitors.

In Boost mode, input current flows continuously into the inductor;

AC ripple component is only proportional to the rate of the

inductor charging, thus, smaller value input capacitors may be

used. It is recommended that an input capacitor of at least 10µF

be used. Ensure the voltage rating of the input capacitor is

suitable to handle the full supply range.

24

FN7709.1

March 24, 2011

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