SAA2003H データシートの表示（PDF） - Philips Electronics

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SAA2003H

Stereo filter and codec

Philips Electronics 

Philips Semiconductors

Stereo filter and codec

Preliminary specification

SAA2003

SUB-BAND SERIAL PASC INTERFACE DATA FORMAT

The PASC data is transferred over the interface described

above using the format shown in Fig.11. Each period of

SBWS spans 64 periods of the bit clock, SBCL, of which

32 SBCL periods are used to transfer PASC data.

The 32 data bits transferred in one period of SBWS make

up a complete sub-band slot, as defined in the DCC

standard. The first 16 data bits (0, 1, 2, .., 15) are

transferred while SBWS is LOW, and the second 16 data

bits (16, 17, 18, .., 31) are transferred while SBWS is

HIGH.

SBEF and URDA are generated by the drive processor

during decode. The presence of the URDA flag causes the

stereo filter codec to mute the audio output data, and lose

audio frame synchronization.

The direction of SBDA is controlled by the SBDIR input,

which is connected to the drive processor.

SYNCDAI signal

SYNCDAI is a pulse of fixed duration which is generated

by the SAA2003 when any of the following conditions

occur:

• Change of bit rate

• Change of sampling frequency

• Change from encode to decode and vice-versa

• Change of FS256 clock source

• Change of I2S bus master

• Reset.

The SYNCDAI signal is used to synchronize the digital

audio input/output interface.

Audio peak level detector

The peak level detector continuously encodes the

maximum amplitude of the audio data samples for each

audio channel until it is reset by the action of reading out

the peak level data. The peak level data can be read by the

SAA2013, and subsequently by the system

microcontroller, or by the microcontroller directly when

SAA2013 is not used.

The peak level data is read via the L3 interface in status

read mode. The first 16 bits of status read transfer the

status bits of SAA2003. The following 32 bits contain the

peak level data. The peak level detector is reset when the

32 bits of peak level data are read.

In encode, the peak level detector can be used to monitor

the data on either SD1 (pre-fade processor) or SD2

(post fade processor). In slave EIAJ input modes the peak

detection is only possible on output SD2. In decode mode,

SD1 must be selected for peak detector input data.

handbook, fuLl3l pMagOeDwEidth

L3CLK

L3DATA

8

15 0

7

16 17

30 31

32 33

Fig.12 Peak level data format during status read.

46 47

MBD625

May 1994

16

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