LH7A400N0G000B5 データシートの表示（PDF） - NXP Semiconductors.
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LH7A400N0G000B5 Datasheet PDF : 63 Pages
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32-Bit System-on-Chip
NXP Semiconductors
LH7A400
Table 3. Functional Pin List (Cont’d)
BGA
PIN
P9
N9
P7
R7
T7
N8
T15
T16
E7
D7
C7
B7
C4
D5
B4
A4
A3
B3
A2
E2
E3
E5
F2
F3
F4
J7
H4
J1
J2
J3
LFBGA
PIN
SIGNAL
P9
LCDENAB/
LCDM
N9 LCDDCLK
M8 LCDVD0
P8 LCDVD1
R8 LCDVD2
T8 LCDVD3
T16 USBDP
R16 USBDN
C7 nPWME0
A6 nPWME1
B6 PWM0
B5 PWM1
A2 ACBITCLK
A1 ACOUT
B2 ACSYNC
E6 ACIN
C3
MMCCLK/
MMSPICLK
B1
MMCCMD/
MMSPIDIN
D4
MMCDATA/
MMSPIDOUT
E1 UARTCTS2
F3 UARTDCD2
G4 UARTDSR2
G5 UARTIRTX1
G6 UARTIRRX1
F1 UARTTX2
G3 UARTRX2
J3 SSPCLK
J6 SSPRX
J7 SSPTX
J2
SSPFRM/
nSSPFRM
DESCRIPTION
LCD TFT Data Enable
LCD STN AC Bias
LCD Data Clock
RESET
STATE
LOW:
LCDENAB
LOW
LCD Video Data Bus
LOW
USB Data Positive (Differential Pair)
Input
USB Data Negative (Differential Pair)
Input
• DC-DC Converter Pulse Width
• Modulator 0 Enable
Input
• DC-DC Converter Pulse Width
• Modulator 1 Enable
Input
• DC-DC Converter Pulse Width
• Modulator 0 Output during normal operation and
Polarity Selection input at reset
Input
• DC-DC Converter Pulse Width
• Modulator 1 Output during normal operation and
Polarity Selection input at reset
Input
• Audio Codec (AC97) Clock
• Audio Codec (ACI) Clock
Input
• Audio Codec (AC97) Output
• Audio Codec (ACI) Output
LOW
• Audio Codec (AC97)
Synchronization
• Audio Codec (ACI) Synchronization
LOW
• Audio Codec (AC97) Input
• Audio Codec (ACI) Input
Input
• MultiMediaCard Clock (20 MHz MAX.)
• MultiMediaCard SPI Mode Clock
LOW:
MMCCLK
• MultiMediaCard Command
• MultiMediaCard SPI Mode Data Input
Input:
MMCCMD
• MultiMediaCard Data
• MultiMediaCard SPI Mode Data Output
Input:
MMCDATA
• UART2 Clear to Send Signal. This pin is an
output for JTAG boundary scan only.
Input
• UART2 Data Carrier Detect Signal. This pin is
output for JTAG boundary scan only.
Input
UART2 Data Set Ready Signal
Input
IrDA Transmit
LOW
IrDA Receive. This pin is an output for JTAG
boundary scan only.
Input
UART2 Transmit Data Output
HIGH
UART2 Receive Data Input. This pin is an output
for JTAG boundary scan only.
Input
Synchronous Serial Port Clock
LOW
Synchronous Serial Port Receive
Input
Synchronous Serial Port Transmit
LOW
Synchronous Serial Port Frame Sync
Input
STANDBY
STATE
LOW
LOW
LOW
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
LOW
Input
Input
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
LOW
Input
OUTPUT
DRIVE
I/O
NOTES
12 mA O
12 mA O
O
O
12 mA
O
O
I/O 10
I/O 10
I
I
8 mA I/O
8 mA I/O
8 mA I/O
8 mA O
8 mA O
I
8 mA O
8 mA I/O
8 mA I/O
I
I
I
8 mA O
I
8 mA O
I
8 mA O
I
8 mA I/O
8 mA I/O
Product data sheet
Rev. 02 — 19 March 2009
11
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