(DVDD = 3.3 V, DVDD2 = 2.5 V, C24MI = 24.5454 MHz, TA = 0 to +70˚C)
PARAMETER
Clock cycle
Pulse width (High)
Pulse width (Low)
Chip select delay
MEMRASZ output delay
MEMCASZ output delay
Write enable delay
Addressing delay
MEMCKE1 to MEMCKE3 output delay
MEML(U)DQM output delay
Data output delay (write cycle)
Data setup delay (read cycle)
Data hold delay (read cycle)
SYMBOL
TMCLK
TMCLKH
TMCLKL
TMCSD
TMRASD
TMCASD
TMWED
TMAD
TMCKED
TMDQMD
TMDD
TMDS
TMDH
CONDITIONS
MIN. TYP. MAX.
20
9
9
0
7
0
7
0
7
0
7
0
7
0
7
0
7
0
7
10
3
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTE
2
2
2
1
2
2
2
2
1
2
2
NOTES :
1. Output load capacity CL = 10 pF
2. Output load capacity CL = 50 pF
LR38666Y
17