LT1460
Applications Information
CL = 1µF. RS should not be made arbitrarily large because
it will limit the load regulation.
Figure 6 to Figure 8 illustrate response in the LT1460-5.
The 1V step from 5V to 4V produces a current step of
1mA or 100µA for RL = 1k or RL = 10k. Figure 7 shows the
response of the reference with no load capacitance.
The reference settles to 5mV (0.1%) in less than 2µs for
a 100µA pulse and to 0.1% in 3µs with a 1mA step. When
load capacitance is greater than 0.01µF, the reference begins
to ring due to the pole formed with the output impedance.
Figure 8 shows the response of the reference to a 1mA
and 100µA load current step with a 0.01µF load capacitor.
Figure 9 to Figure 11 illustrate response of the LT1460-10.
The 1V step from 10V to 9V produces a current step of
1mA or 100µA for RL = 1k or RL = 10k. Figure 10 shows
the response of the reference with no load capacitance.
The reference settles to 10mV (0.1%) in 0.4µs for a 100µA
pulse and to 0.1% in 0.8µs with a 1mA step. When load
capacitance is greater than 0.01µF, the reference begins
to ring due to the pole formed with the output impedance.
Figure 11 shows the response of the reference to a 1mA and
100µA load current step with a 0.01µF load capacitor.
VIN = 5V
CIN
0.1µF
LT1460-5
VOUT
RL
CL
VGEN
5V
4V
1460 F06
Figure 6. Response Time Test Circuit
VIN = 12.5V
CIN
0.1µF
LT1460-10
VOUT
RL
CL
VGEN
10V
9V
1460 F09
Figure 9. Response Time Test Circuit
VGEN
VOUT
VOUT
2µs/DIV
Figure 7. CL = 0
5V
4V
RL = 10k
RL = 1k
1460 F07
VGEN
VOUT
VOUT
2µs/DIV
Figure 10. CL = 0
10V
9V
RL = 10k
RL = 1k
1460 F10
VGEN
VOUT
VOUT
16
5V
4V
RL = 10k
RL = 1k
10µs/DIV
1460 F08
Figure 8. CL = 0.01µF
VGEN
VOUT
VOUT
10V
9V
RL = 10k
RL = 1k
10µs/DIV
1460 F11
Figure 11. CL = 0.01µF
1460fc