LTC1735IGN データシートの表示（PDF） - Linear Technology
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LTC1735IGN Datasheet PDF : 32 Pages
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LTC1735
APPLICATIO S I FOR ATIO
Although all dissipative elements in the circuit produce
losses, 4 main sources usually account for most of the
losses in LTC1735 circuits: 1) VIN current, 2)␣ INTVCC
current, 3) I2R losses, 4) Topside MOSFET transition
losses.
1) The VIN current is the DC supply current given in the
electrical characteristics which excludes MOSFET driver
and control currents. VIN current results in a small (<0.1%)
loss that increases with VIN.
2) INTVCC current is the sum of the MOSFET driver and
control currents. The MOSFET driver current results from
switching the gate capacitance of the power MOSFETs.
Each time a MOSFET gate is switched from low to high to
low again, a packet of charge dQ moves from INTVCC to
ground. The resulting dQ/dt is a current out of INTVCC that
is typically much larger than the control circuit current. In
continuous mode, IGATECHG = f(QT+QB), where QT and QB
are the gate charges of the topside and bottom-side
MOSFETs.
Supplying INTVCC power through the EXTVCC switch input
from an output-derived or other high efficiency source will
scale the VIN current required for the driver and control
circuits by a factor of (Duty Cycle)/(Efficiency). For ex-
ample, in a 20V to 5V application, 10mA of INTVCC current
results in approximately 3mA of VIN current. This reduces
the mid-current loss from 10% or more (if the driver was
powered directly from VIN) to only a few percent.
3) I2R losses are predicted from the DC resistances of the
MOSFET, inductor and current shunt. In continuous mode
the average output current flows through L and RSENSE,
but is “chopped” between the topside main MOSFET and
the synchronous MOSFET. If the two MOSFETs have
approximately the same RDS(ON), then the resistance of
one MOSFET can simply be summed with the resistances
of L and RSENSE to obtain I2R losses. For example, if each
RDS(ON) = 0.03Ω, RL = 0.05Ω and RSENSE = 0.01Ω, then
the total resistance is 0.09Ω. This results in losses ranging
from 2% to 9% as the output current increases from 1A to
5A for a 5V output, or a 3% to 14% loss for a 3.3V output.
Effeciency varies as the inverse square of VOUT for the
same external components and output power level. I2R
losses cause the efficiency to drop at high output currents.
4) Transition losses apply only to the topside MOSFET(s)
and only become significant when operating at high input
voltages (typically 12V or greater). Transition losses can
be estimated from:
Transition Loss = (1.7) VIN2 IO(MAX) CRSS f
Other “hidden” losses such as copper trace and internal
battery resistances can account for an additional 5% to
10% efficiency degradation in portable systems. It is very
important to include these “system” level losses in the
design of a system. The internal battery and fuse resis-
tance losses can be minimized by making sure that CIN has
adequate charge storage and very low ESR at the switch-
ing frequency. A 25W supply will typically require a
minimum of 20µF to 40µF of capacitance having a maxi-
mum of 0.01Ω to 0.02Ω of ESR. Other losses including
Schottky conduction losses during dead-time and induc-
tor core losses generally account for less than 2% total
additional loss.
Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in load current.
When a load step occurs, VOUT shifts by an amount equal
to ∆ILOAD (ESR), where ESR is the effective series resis-
tance of COUT. ∆ILOAD also begins to charge or discharge
COUT, generating the feedback error signal that forces the
regulator to adapt to the current change and return VOUT
to its steady-state value. During this recovery time VOUT
can be monitored for excessive overshoot or ringing,
which would indicate a stability problem. OPTI-LOOP
compensation allows the transient response to be opti-
mized over a wide range of output capacitance and ESR
values. The availability of the ITH pin not only allows
optimization of control loop behavior but also provides a
DC coupled and AC filtered closed loop response test
point. The DC step, rise time and settling at this test point
truly reflects the closed loop response. Assuming a pre-
dominantly second order system, phase margin and/or
damping factor can be estimated using the percentage of
overshoot seen at this pin. The bandwidth can also be
estimated by examining the rise time at the pin. The ITH
external components shown in the Figure␣ 1 circuit will
provide an adequate starting point for most applications.
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