TEST CIRCUITS
Load Circuits for Access Timing
DN
1k
25pF
5V
1k
DN
25pF
(A) Hi-Z TO VOH AND VOL TO VOH
(B) Hi-Z TO VOL AND VOH TO VOL
18545 TC01
TI I G DIAGRA S
CONVST
t1 (For Short Pulse Mode)
t1
50%
50%
18545 TD01
t3, t4, t5 (SCK Timing)
t4
t5
SCK
t3
18545 TD03
t8 (SDO Valid After RD )
t8
RD
0.4V
Hi-Z
SDO
2.4V
0.4V
18545 TD05
LTC1854/LTC1855/LTC1856
Load Circuits for Output Float Delay
DN
1k
5V
1k
DN
25pF
25pF
(A) VOH TO Hi-Z
(B) VOL TO Hi-Z
18545 TC02
CONVST
t2 (CONVST to BUSY Delay)
t2
2.4V
BUSY
0.4V
18545 TD02
t6 (Delay Time, SCK to SDO Valid)
t7 (Time from Previous Data Remains Valid After SCK )
t6
t7
SCK
0.4V
SDO
2.4V
0.4V
18545 TD04
t9 (RD to SCK Setup Time)
t9
RD
0.4V
SCK
2.4V
18545 TD06
185456fa
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