LTC3215
APPLICATIONS INFORMATION
when comparing different capacitors, it is often more ap-
propriate to compare the amount of achievable capacitance
for a given case size rather than comparing the specified
capacitance value. For example, over rated voltage and
temperature conditions, a 1µF, 10V, Y5V ceramic capaci-
tor in a 0603 case may not provide any more capacitance
than a 0.22µF, 10V, X7R available in the same case. The
capacitor manufacturer’s data sheet should be consulted
to determine what value of capacitor is needed to ensure
minimum capacitances at all temperatures and voltages.
Table 2 shows a list of ceramic capacitor manufacturers
and how to contact them.
Table 2. Recommended Capacitor Vendors
AVX
www.avxcorp.com
Kemet
www.kemet.com
Murata
www.murata.com
Taiyo Yuden
www.t-yuden.com
Vishay
www.vishay.com
TDK
www.tdk.com
Layout Considerations and Noise
Due to its high switching frequency and the transient
currents produced by the LTC3215, careful board layout
is necessary. A true ground plane and short connections
to all capacitors will improve performance and ensure
proper regulation under all conditions. An example of
such a layout is shown in Figure 4.
C1
CCPO
PIN 1
C2
CIN
3215 F04
Figure 4. Example Board Layout
The flying capacitor pins C1+, C2+, C1– and C2– will have
very high edge rate waveforms. The large dv/dt on these
pins can couple energy capacitively to adjacent PCB runs.
Magnetic fields can also be generated if the flying capacitors
are not close to the LTC3215 (i.e., the loop area is large).
To decouple capacitive energy transfer, a Faraday shield
may be used. This is a grounded PCB trace between the
sensitive node and the LTC3215 pins. For a high quality
AC ground, it should be returned to a solid ground plane
that extends all the way to the LTC3215.
The following guidelines should be followed when design-
ing a PCB layout for the LTC3215.
• The Exposed Pad should be soldered to a large copper
plane that is connected to a solid, low impedance ground
plane using plated, through-hole vias for proper heat
sinking and noise protection.
• Input and output capacitors (CIN and CCPO) must also
be placed as close to the part as possible.
• The flying capacitors must also be placed as close to
the part as possible. The traces running from the pins
to the capacitor pads should be as wide as possible.
• VIN, CPO and ILED traces must be made as wide as
possible. This is necessary to minimize inductance,
as well as provide sufficient area for high current ap-
plications.
• LED pads must be large and should be connected to
as much solid metal as possible to ensure proper heat
sinking.
Power Efficiency
To calculate the power efficiency (η) of a white LED
driver chip, the LED power should be compared to the
input power. The difference between these two numbers
represents lost power whether it is in the charge pump
or the current sources. Stated mathematically, the power
efficiency is given by:
η ≡ PLED
PIN
(4)
3215fc
10