LTC6082IGN-PBF データシートの表示（PDF） - Linear Technology

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LTC6082IGN-PBF

Precision Dual/Quad CMOS Rail-to-Rail Input/Output Amplifiers

Linear Technology 

PACKAGE DESCRIPTION

DD Package

10-Lead Plastic DFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1699 Rev B)

LTC6081/LTC6082

0.70 p0.05

3.55 p0.05

1.65 p0.05

2.15 p0.05 (2 SIDES)

PACKAGE

OUTLINE

0.25 p 0.05

0.50

BSC

2.38 p0.05

(2 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

R = 0.125

TYP

6

0.40 p 0.10

10

3.00 p0.10 1.65 p 0.10

(4 SIDES) (2 SIDES)

PIN 1

TOP MARK

(SEE NOTE 6)

0.200 REF

0.75 p0.05

0.00 – 0.05

(DD) DFN REV B 0309

5

1

0.25 p 0.05

0.50 BSC

2.38 p0.10

(2 SIDES)

BOTTOM VIEW—EXPOSED PAD

NOTE:

1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).

CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE

TOP AND BOTTOM OF PACKAGE

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