LTC6082IGN-PBF データシートの表示（PDF） - Linear Technology

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LTC6082IGN-PBF

Precision Dual/Quad CMOS Rail-to-Rail Input/Output Amplifiers

Linear Technology 

LTC6081/LTC6082

PACKAGE DESCRIPTION

DHC Package

16-Lead Plastic DFN (5mm × 3mm)

(Reference LTC DWG # 05-08-1706)

0.65 ±0.05

3.50 ±0.05

1.65 ±0.05

2.20 ±0.05 (2 SIDES)

PACKAGE

OUTLINE

0.25 ± 0.05

0.50 BSC

4.40 ±0.05

(2 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

5.00 ±0.10

(2 SIDES)

9

R = 0.20

TYP

R = 0.115

TYP

0.40 ± 0.10

16

3.00 ±0.10 1.65 ± 0.10

(2 SIDES) (2 SIDES)

PIN 1

TOP MARK

(SEE NOTE 6)

0.200 REF

0.75 ±0.05

0.00 – 0.05

8

1

0.25 ± 0.05

0.50 BSC

4.40 ±0.10

(2 SIDES)

BOTTOM VIEW—EXPOSED PAD

NOTE:

1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJED-1) IN JEDEC

PACKAGE OUTLINE MO-229

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE

TOP AND BOTTOM OF PACKAGE

PIN 1

NOTCH

(DHC16) DFN 1103

60812fc

16

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