M2V28S20ATP-7L データシートの表示（PDF） - Mitsumi
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M2V28S20ATP-7L Datasheet PDF : 51 Pages
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SDRAM (Rev. 1.0E)
Nov. '99
MITSUBISHI LSIs
128M Synchronous DRAM
M2V28S20ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 8,388,608-WORD x 4-BIT)
M2V28S30ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 4,194,304-WORD x 8-BIT)
M2V28S40ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 16-BIT)
CLK
Command
A0-9
A10
A11
BA0,1
DQ
CLK
Command
A0-9
A10
A11
BA0,1
DQ
CLK
Command
CL=3 DQ
CL=2 DQ
Multi Bank Interleaving READ (BL=4, CL=3)
ACT
Xa
tRCD
READ ACT
Y Xb
READ PRE
Y
Xa
0 Xb
00
Xa
Xb
00
00 10
10 00
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2
/CAS latency
Burst Length
READ with Auto-Precharge (BL=4, CL=3)
ACT
READ
tRCD
Xa
Y
BL + tRP
BL
ACT
tRP
Xa
Xa
1
Xa
Xa
Xa
00
00
00
Qa0 Qa1 Qa2 Qa3
Internal precharge start
READ Auto-Precharge Timing (BL=4)
ACT
READ
BL
Qa0 Qa1 Qa2 Qa3
Qa0 Qa1 Qa2 Qa3
Internal Precharge Start Timing
MITSUBISHI ELECTRIC
18
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