MITSUBISHI MICROCOMPUTERS
M37207MF-XXXSP/FP, M37207M8-XXXSP
M37207EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
and ON-SCREEN DISPLAY CONTROLLER
FUNCTIONAL DESCRIPTION
Central Processing Unit (CPU)
This microcomputer uses the standard 740 Family instruction set.
Refer to the table of 740 Family addressing modes and machine
instructions or the SERIES 740 <Software> User’s Manual for de-
tails on the instruction set.
Machine-resident 740 Family instructions are as follows:
The FST, SLW instruction cannot be used.
The MUL, DIV, WIT and STP instructions can be used.
CPU Mode Register
The CPU mode register contains the stack page selection bit and
internal system clock selection bit. The CPU mode register is allo-
cated at address 00FB16.
CPU Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
1 0 0 CPU mode register (CPUM) (CM) [Address 00FB 16]
B
Name
0, 1 Processor mode bits
(CM0, CM1)
Functions
b1 b0
0 0: Single-chip mode
0 1:
1 0: Not available
1 1:
After reset R W
0 RW
2 Stack page selection 0: 0 page
bit (CM2) (See note 1) 1: 1 page
1 RW
3 Fix these bits to “1.”
1 RW
4 Internal system clock
output selection bit
(CM4) (See note 2)
0: Output is stopped
1: Internal system
clock φ output
1 RW
5 XCOUT drivability
selection bit (CM5)
0: LOW drive
1: HIGH drive
6 Main Clock (X IN–XOUT) 0: Oscillating
stop bit
1: Stopped
(CM6)
1 RW
0 RW
7 Internal system clock 0: XIN–XOUT selected
0 RW
selection bit
(high-speed mode)
(CM7)
1: XCIN–XCOUT selected
(high-speed mode)
Fig. 3. CPU Mode Register
Notes 1: This bit is set to “1” after the reset release.
2: The internal system clock φ stops at HIGH.
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