M5M44265CJ-6S データシートの表示（PDF） - Mitsumi
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M5M44265CJ-6S Datasheet PDF : 31 Pages
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MITSUBISHI LSIs
M5M44265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
2. Burst refresh during Read/Write operation
(A) Timing diagram
Read / Write
tNSB
Self Refresh
tRASS ≥100µs
RAS
first
refresh cycles
refresh cycles 511 cycles
Table 3
Read / Write Cycle
CBR burst
refresh
RAS only
burst refresh
Read / Write
Self Refresh
tNSB ≤ 8.2ms
Self Refresh
Read / Write
tSNB ≤ 8.2ms
tNSB+tSNB ≤ 8.2ms
Read / Write
tSNB
refresh cycles
511 cycles
last
refresh cycles
(B) Definition of burst refresh
8.2ms
RAS
refresh cycles
512 cycles
read/write cycles
Definition of CBR burst refresh
The CBR burst refresh performs more than 512 continuous
CBR cycles within 8.2 ms.
Definition of RAS only burst refresh
All combination of nine row address signals (A0~A8) are
selected during 512 continuous RAS only refresh cycles
within 8.2 ms.
2.1 CBR burst refresh
Switching from read/write operation to self refresh operation.
The time interval tNSB from the falling edge of RAS signal in
the first CBR refresh cycle during read/write operation period
to the falling edge of RAS signal at the start of self refresh
operation should be set within 8.2 ms.
Switching from self refresh operation to read/write operation.
The time interval tSNB from the rising edge of RAS signal at
the end of self refresh operation to the falling edge of RAS
signal in the last CBR refresh cycle during read/write operation
period should be set within 8.2 ms.
2.2 RAS only burst refresh
Switching from read/write operation to self refresh operation.
The time interval from the falling edge of RAS signal in the
first RAS only refresh cycle during read/write operation period
to the falling edge of RAS signal at the start of self refresh
operation should be set within tNSB (shown in table 3).
Switching from self refresh operation to read/write operation.
The time interval from the rising edge of RAS signal at the end
of self refresh operation to the falling edge of RAS signal in
the last RAS only refresh cycle during read/write operation
period should be set within tSNB (shown in table 3).
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