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MAX17083 データシートの表示(PDF) - Maxim Integrated

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MAX17083 Datasheet PDF : 15 Pages
First Prev 11 12 13 14 15
Low-Voltage, Internal Switch,
Step-Down Regulator
For the MAX17083 system (IN) supply, ceramic capaci-
tors are preferred due to their resilience to inrush surge
currents typical of systems, and due to their low para-
sitic inductance, which helps reduce the high-frequen-
cy ringing on the IN supply when the internal MOSFETs
are turned off. Choose an input capacitor that exhibits
less than +10°C temperature rise at the RMS input cur-
rent for optimal circuit longevity.
BST Capacitors
The boost capacitor (CBST) must be selected large
enough to handle the gate charging requirements of
the high-side MOSFETs. For these low-power applica-
tions, 0.1µF ceramic capacitors work well.
Applications Information
Duty-Cycle Limits
Minimum Input Voltage
The minimum input operating voltage (dropout voltage)
is restricted by the maximum duty-cycle specification
(see the Electrical Characteristics table). For the best
dropout performance, use the slowest switching fre-
quency setting (FREQ = GND). However, keep in mind
that the transient performance gets worse as the step-
down regulators approach the dropout voltage, so bulk
output capacitance must be added (see the voltage
sag and soar equations in the SMPS Design Procedure
section). The absolute point of dropout occurs when the
inductor current ramps down during the off-time
(ΔIDOWN) as much as it ramps up during the on-time
(ΔIUP). This results in a minimum operating voltage
defined by the following equation:
( ) VIN(MIN)
=
VOUT
+
VCHG
+
h⎝⎜
1
DMAX
- 1⎠⎟
VOUT + VDIS
where VCHG and VDIS are the parasitic voltage drops in
the charge and discharge paths, respectively. A rea-
sonable minimum value for h is 1.5, while the absolute
minimum input voltage is calculated with h = 1.
Maximum Input Voltage
The MAX17083 controller includes a minimum on-time
specification, which determines the maximum input
operating voltage that maintains the selected switching
frequency (see the Electrical Characteristics table).
Operation above this maximum input voltage results in
pulse skipping to avoid overcharging the output. At the
beginning of each cycle, if the output voltage is still
above the feedback threshold voltage, the controller
does not trigger an on-time pulse, effectively skipping a
cycle. This allows the controller to maintain regulation
above the maximum input voltage, but forces the con-
troller to effectively operate with a lower switching fre-
quency. This results in an input threshold voltage at
which the controller begins to skip pulses (VIN(SKIP)):
VIN(SKIP)
=
VOUT
1
fOSCt ON(MIN)
where fOSC is the switching frequency selected by FREQ.
PCB Layout Guidelines
Careful PCB layout is critical to achieving low switching
losses and clean, stable operation. The switching power
stage requires particular attention. If possible, mount all
the power components on the top side of the board,
with their ground terminals flush against one another.
Follow the MAX17083 Evaluation Kit layout and use the
following guidelines for good PCB layout:
• Keep the high-current paths short, especially at the
ground terminals. This practice is essential for sta-
ble, jitter-free operation.
• Keep the power traces and load connections short.
This practice is essential for high efficiency. Using
thick copper PCBs (2oz vs. 1oz) can enhance full-
load efficiency by 1% or more. Correctly routing
PCB traces is a difficult task that must be
approached in terms of fractions of centimeters,
where a single milliohm of excess trace resistance
causes a measurable efficiency penalty.
• When trade-offs in trace lengths must be made, it is
preferable to allow the inductor charging path to be
made longer than the discharge path. For example,
it is better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the low-
side MOSFET or between the inductor and the out-
put filter capacitor.
• Route high-speed switching nodes (BST and LX)
away from sensitive analog areas (REF and FB).
14 ______________________________________________________________________________________

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