622Mbps, Low-Power, 3.3V Clock-Recovery
and Data-Retiming IC with Limiting Amplifier
AC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +5.5V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V and TA = +25°C.)
(Notes 3, 4)
PARAMETER
Differential Input Voltage Range
Input Referred Noise
Power-Detect Hysteresis
Limiting Amplifier Small-Signal Bandwidth
RSSI Output Voltage
Threshold Voltage
RSSI Linearity
SYMBOL
VID
VN
BW
VTH
CONDITIONS
BER < 10-10, ADI inputs (Note 5)
ADI inputs
VRELEASE = 3.6mVp-p (Note 6)
(Note 7)
(ADI+) - (ADI-) = 2mVp-p
(ADI+) - (ADI-) = 20mVp-p
VRELEASE = 3.6mVp-p
(ADI+) - (ADI-) = 2mVp-p to 50mVp-p
MIN
0.003
2
TYP
100
3
800
1.36
1.93
1.40
±0.7
MAX
1.2000
5
UNITS
Vp-p
µV
dB
MHz
V
V
%
RSSI Slope
(ADI+) - (ADI-) = 2mVp-p to
50mVp-p (Note 8)
29
mV/dB
Loop Bandwidth
Jitter Generation (Note 9)
Jitter-Transfer Peaking
Jitter Tolerance (Note 9)
CF = 2.2µF, RF = 52.3Ω
CF = 0.022µF, RF = 523Ω
CF = 2.2µF, RF = 52.3Ω
CF = 0.022µF,CRFF==05.02232ΩµF
RF = 52.3Ω, CF = 2.2µF
f = 10kHz
RF = 52.3Ω,
CF = 2.2µF
f = 25kHz
f = 250kHz
f = 1MHz
350
3.5
13
6
0.08
8
1.50 3.35
0.25 0.60
0.20 0.50
kHz
MHz
mUI
dB
UI
Maximum Consecutive Input
Run Length (1 or 0)
1000
Bits
Serial Clock-to-Q Delay
Serial Clock Frequency
tCLK-Q
fSCLK
195 275 370
622.08
ps
MHz
Note 3: AC parameters are guaranteed by design and characterization.
Note 4: The MAX3675 is characterized with a PRBS of 223 - 1 maintaining a BER of ≤ 10-10 having a confidence level of 99.9%.
Note 5: A lower minimum input voltage of 2mVp-p is achievable; however, the LOP hysteresis is not guaranteed below 3.6mVp-p.
Note 6: Hysteresis = 20log(VRELEASE / VASSERT).
Note 7: Small-signal bandwidth cannot be measured directly.
Note 8: RSSI slope = [VRSSI2 - VRSSI1] / [20log (VID2 / VID1)].
Note 9: 1UI = 1 unit interval = (622.08MHz)-1 = 1.608ns.
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