MAX8529 データシートの表示（PDF） - Maxim Integrated

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MAX8529

1.5MHz Dual 180° Out-of-Phase PWM Step-Down Controller with POR

Maxim Integrated 

1.5MHz Dual 180° Out-of-Phase

PWM Step-Down Controller with POR

600kΩ. In adjustable mode, the current-limit threshold

across the low-side MOSFET is precisely 1/10th the

voltage seen at ILIM_. However, the current-limit

threshold defaults to 100mV when ILIM is connected to

VL. The logic threshold for switchover to this 100mV

default value is approximately VL - 0.5V.

Adjustable foldback current limit reduces power dissi-

pation during short-circuit conditions (see the Design

Procedure section).

Carefully observe the PC board layout guidelines to

ensure that noise and DC errors do not corrupt the cur-

rent-sense signals seen by LX_ and PGND. The IC

must be mounted close to the low-side MOSFET with

short direct traces making a Kelvin sense connection

so that trace resistance does not add to the intended

sense resistance of the low-side MOSFET.

Undervoltage Lockout and Startup

If VL drops below 4.5V, the MAX8529 assumes that the

supply and reference voltages are too low to make valid

decisions and activates the undervoltage lockout (UVLO)

circuitry, which forces DH low and DL high to inhibit

switching. RST is also forced low during UVLO. After VL

rises above 4.5V, the controller powers up the outputs.

Enable (EN), Soft-Start, and Soft-Stop

Pull EN high to enable or low to shut down both regula-

tors. During shutdown the supply current drops to 1mA

(max), LX enters a high-impedance state (DH_ con-

nected to LX_, and DL_ connected to PGND), and

COMP_ is discharged to GND through a 17Ω resistor.

VL and REF remain active in shutdown. For “always-on”

operation, connect EN to VL.

On the rising edge of EN both controllers enter soft-

start. Soft-start gradually ramps up to the reference

voltage seen by the error amplifier in order to control

the outputs’ rate of rise and reduce input surge cur-

rents during startup. The soft-start period is 1024 clock

cycles (1024/fSW), and the internal soft-start DAC

ramps up the voltage in 64 steps. The output reaches

regulation when soft-start is completed. On the falling

edge of EN both controllers simultaneously enter soft-

stop, which reverses the soft-start ramp. The part

enters shutdown after soft-stop is complete.

Reset Output

RST is an open-drain output. RST pulls low when either

output falls below 90% of its nominal regulation voltage.

Once both outputs exceed 90% of their nominal regulation

voltages and both soft-start cycles are completed, RST

goes high impedance. To obtain a logic-voltage output,

connect a pullup resistor from RST to the logic supply

voltage. A 100kΩ resistor works well for most applications.

If unused, leave RST grounded or unconnected.

Clock Synchronization (SYNC, CKO)

SYNC serves two functions: SYNC selects the clock

output (CKO) type used to synchronize slave con-

trollers, or it serves as a clock input so the MAX8529

can be synchronized with an external clock signal. This

allows the MAX8529 to function as either a master or

slave. CKO provides a clock signal synchronized to the

MAX8529’s switching frequency, allowing either in-

phase (SYNC = GND) or 90-degrees out-of-phase

(SYNC = VL) synchronization of additional DC-to-DC

controllers (Figure 5). The MAX8529 supports the fol-

lowing three operating modes:

• SYNC = GND: The CKO output frequency equals

REG1’s switching frequency (fCKO = fDH1) and the

CKO signal is in phase with REG1’s switching fre-

quency. This provides 2-phase operation when syn-

chronized with a second slave controller.

• SYNC = VL: The CKO output frequency equals two

times REG1’s switching frequency (fCKO = 2fDH1)

and the CKO signal is phase shifted by 90 degrees

with respect to REG1’s switching frequency. This

provides 4-phase operation when synchronized with

a second MAX8529 (slave controller).

• SYNC Driven by External Oscillator: The controller

generates the clock signal by dividing down the

SYNC input signal, so that the switching frequency

equals half the synchronization frequency (fSW =

fSYNC / 2). REG1’s conversion cycles initiate on the

rising edge of the internal clock signal. The CKO out-

put frequency and phase match REG1’s switching

frequency (fCKO = fDH1) and the CKO signal is in

phase. Note that the MAX8529 still requires ROSC

when SYNC is externally clocked and the internal

oscillator frequency should be set to 50% of the syn-

chronization frequency (fOSC = 0.5 fSYNC).

Thermal-Overload Protection

Thermal-overload protection limits total power dissipation

in the MAX8529. When the device’s die junction tempera-

ture exceeds TJ = +160°C, an on-chip thermal sensor

shuts down the device, forcing DL_ and DH_ low, allow-

ing the IC to cool. The thermal sensor turns the part on

again after the junction temperature cools by 10°C.

During thermal shutdown, the regulators shut down, RST

goes low, and soft-start is reset. If the VL linear-regulator

output is short-circuited, thermal-overload protection is

triggered.

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