Single/Dual LVDS Line Receivers with
Ultra-Low Pulse Skew in SOT23
Test Circuit Diagrams
GENERATOR
50Ω
IN_+
IN_- R
50Ω
OUT_
CL
Figure 1. Receiver Propagation Delay and Transition Time Test Circuit
IN_-
IN_+
OUT_
0V DIFFERENTIAL VID = 200mV
tPLHD
80%
50%
20%
tTLH
Figure 2. Receiver Propagation Delay and Transition Time Waveforms
+1.3V
+1.2V
+1.1V
tPHLD
80%
VOH
50%
20%
VOL
tTHL
4 _______________________________________________________________________________________