MAXQ3120-FFN データシートの表示（PDF） - Dallas Semiconductor -> Maxim Integrated

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MAXQ3120-FFN

High-Precision ADC Mixed-Signal Microcontroller

Dallas Semiconductor -> Maxim Integrated 

High-Precision ADC

Mixed-Signal Microcontroller

ELECTRICAL CHARACTERISTICS (continued)

(DVDD, AVDD = VRST to 3.6V, VREF = 1.25V (external), fHFXIN = 8MHz, TA = -40°C to +85°C, unless otherwise noted.) (Note 1)

PARAMETER

SYMBOL

CONDITIONS

MIN TYP MAX UNITS

INTERNAL REFERENCE

Reference Output Voltage

1.25

V

Reference-Output Temperature

Coefficient

Load Regulation

LCD INTERFACE

LCD Reference Voltage

LCD Bias Voltage 1

LCD Bias Voltage 2

With VREF bandgap trimming

(ATRM[4:0] = 01111b)

IREF = ±2µA, CL = 12pF

VLCD

VLCD1

Guaranteed by design

VLCD2 Guaranteed by design

LCD Adjustment Voltage (Note 7)

LCD Bias Resistor

LCD Adjust Resistor

LCD Segment Voltage

CLOCK SOURCE

External Crystal Frequency

REAL-TIME CLOCK

RTC Input Frequency

JTAG/FLASH PROGRAMMING

JTAG Clock Rate

Flash Erase Time

Flash Programming Time

Write/Erase Cycles

Data Retention

VADJ

RLCD

RLADJ

VSEGxx

Guaranteed by design

LRA4:LRA0 = 0

Segment is driven at VLCD; VLCD = 3V,

ISEGxx = -3µA, guaranteed by design

Segment is driven at VLCD1; VLCD1 = 2V,

ISEGxx = -3µA, guaranteed by design

Segment is driven at VLCD2; VLCD2 = 1V,

ISEGxx = -3µA, guaranteed by design

Segment is driven at VADJ; VADJ = 0V,

ISEGxx = +3µA, guaranteed by design

fHFXIN

f32KIN 32kHz watch crystal

fTCK

Mass erase

Page erase

±120

±35

±50

ppm/°C

±500 µV/µA

DVDD

V

VADJ + 2/3

V

(VLCD - VADJ)

VADJ + 1/3

V

(VLCD - VADJ)

0

0.4 x

VLCD

V

20

kΩ

40

kΩ

VLCD -

0.02

VLCD

V

VLCD1 -

0.02

VLCD1

V

VLCD2 -

0.02

VLCD2

V

VADJ

0.1

V

1

8

MHz

32.768

kHz

sysclk / 8

904

313

17

1,000,000

20

ms

µs

Cycles

Years

Note 1: Specifications to -40°C are guaranteed by design and not production tested. All typical values are guaranteed by design

characterization and are not production tested.

Note 2: Tested with TA = +25°C, DVDD = 3.3V, and all peripherals inactive except for port pins.

Note 3: These numbers are guaranteed by design and are not tested.

Note 4: Can be calculated as (fHFXIN / 6).

Note 5: Can be calculated as 6 / (fHFXIN x CIN).

Note 6: Can be calculated as 12 / (fHFXIN x CIN).

Note 7: Assumes that no external components are connected to VLCD, VLCD1, VLCD2, or VADJ.

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