MC100E241FN データシートの表示（PDF） - ON Semiconductor
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MC100E241FN Datasheet PDF : 8 Pages
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MC10E241, MC100E241
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
SEL0 NC D7 D6 D5 VCCO Q7
S-IN
25 24 23 22 21 20 19
SEL1 26
18 Q6
D0
CLK 27
17 Q5
MR 28
16 VCC
VEE
1
S-IN 2
Pinout: 28-Lead PLCC
(Top View)
15 NC
14 VCCO
D1 – D6
D0 3
13 Q4
D1 4
12 Q3
5 6 7 8 9 10 11
D7
D2 D3 D4 VCCO Q0 Q1 Q2
* All VCC and VCCO pins are tied together on the die.
Warning: All VCC, VCCO, and VEE pins must be externally
connected to Power Supply to guarantee proper operation.
HOLD/LOAD
SHIFT
CLK
MR
LOGIC DIAGRAM
1
1
DQ
0
0
R
1
1
0
0
BITS 1-6
DQ
R
1
1
DQ
0
0
R
PIN DESCRIPTION
PIN
D0 – D7
S-IN
SEL0
SEL1
CLK
MR
Q0 – Q7
VCC, VCCO
VEE
NC
FUNCTION
ECL Parallel Date Inputs
ECL Serial Data Inputs
ECL SHIFT Control
ECL HOLD/LOAD Control
ECL Clock
ECL Master Reset
ECL Data Outputs
Positive Supply
Negative Supply
No Connect
FUNCTION TABLE
MR
SEL0
1
X
0
1
0
0
0
0
X = Don’t Care
SEL1
X
X
1
0
Function
Outputs LOW
Shift Data
Hold Data
Load Data
Q0
Q1 – Q6
Q7
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