MC100EP139DWG データシートの表示（PDF） - ON Semiconductor

部品番号

コンポーネント説明

メーカー

MC100EP139DWG

3.3V / 5VECL ÷2/4, ÷4/5/6 Clock Generation Chip

ON Semiconductor 

MC10EP139, MC100EP139

VCC Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 VEE

20 19 18 17 16 15 14 13 12 11

1 2 3 4 5 6 7 8 9 10

Warning: All VCC and VEE pins must be externally connected to

Power Supply to guarantee proper operation.

Figure 1. 20−Lead Pinout (Top View)

Table 1. PIN DESCRIPTION

PIN

FUNCTION

CLK*, CLK*

ECL Differential Clock Inputs

EN*

ECL Sync Enable

MR*

ECL Master Reset

VBB

Q0, Q1, Q0, Q1

ECL Reference Output

ECL Differential B2/4 Outputs

Q2, Q3, Q2, Q3

ECL Differential B4/5/6 Outputs

DIVSELa*

ECL Frequency Select Input B2/4

DIVSELb0*

ECL Frequency Select Input B4/5/6

DIVSELb1

ECL Frequency Select Input B4/5/6

VCC

ECL Positive Supply

VEE

ECL Negative Supply

EP

Exposed Pad

*Pins will default low when left open.

EN VCC VCC Q0 Q0

20 19 18 17 16

Exposed Pad

DIVSELb0 1

CLK 2

CLK 3

VBB 4

MR 5

MC10/100EP139

15 Q1

14 Q1

13 Q2

12 Q2

11 Q3

6

7 8 9 10

NOTE:

VCC DIVSELb1 DIVSELa VEE Q3

The Exposed Pad (EP) on package bottom must be attached to a heat−sinking conduit.

The Exposed Pad may only be electrically connected to VEE.

Figure 1. QFN−20 Pinout (Top View)

http://onsemi.com

2

Share Link: