MC10EP51DTG(2012) データシートの表示（PDF） - ON Semiconductor

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MC10EP51DTG
(Rev.:2012)

3.3V / 5V ECL D Flip-Flop with Reset and Differential Clock

ON Semiconductor 

MC10EP51, MC100EP51

1100

1000

900

800

700

600

500

400

300

200

ÉÉÉÉÉ 100

(JITTER)

ÉÉÉÉÉ 0

0

1000

2000

3000

4000

FREQUENCY (MHz)

Figure 2. Fmax/Jitter

11

10

Measured

Simulated 9

8

7

6

5

ÉÉ234 ÉÉ

1

5000

6000

Q

Driver

Device

Q

Zo = 50 W

Zo = 50 W

50 W

50 W

D

Receiver

Device

D

VTT

VTT = VCC − 2.0 V

Figure 3. Typical Termination for Output Driver and Device Evaluation

(See Application Note AND8020/D − Termination of ECL Logic Devices.)

Round Sprocket Holes

Designations

Quadrant A = Upper Left

Quadrant B = Upper Right

Quadrant C = Lower Left

Quadrant D = Lower Right

Quadrant

A

Quadrant

B

Quadrant

C

Quadrant

D

User Direction

of Unreeling

Figure 4. Tape and Reel Pin 1 Quadrant Orientation

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