MC14536BDW データシートの表示（PDF） - Motorola => Freescale

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MC14536BDW

Programmable Timer

Motorola => Freescale 

PULSE

GEN.

PULSE

GEN.

CLOCK

+V

16

6 8–BYPASS VDD

9A

OUT 1

4

10 B

11 C

12 D

2 RESET

14 OSC INH

OUT 2

5

15 MONO–IN

1 SET

7 CLOCK INH

3 IN1

VSS DECODE OUT

13

8

IN1

SET

CLOCK INH

DECODE OUT

POWER UP

NOTE: When power is first applied to the device, Decode Out can be either at a high or low state.

On the rising edge of a Set pulse the output goes high if initially at a low state. The output

remains high if initially at a high state. Because Clock Inh is held high, the clock source on

the input pin has no effect on the output. Once Clock Inh is taken low, the output goes low

on the first negative clock transition. The output returns high depending on the 8–Bypass,

A, B, C, and D inputs, and the clock input period. A 2n frequency division (where n = the

number of stages selected from the truth table) is obtainable at Decode Out. A 20–divided

output of IN1 can be obtained at OUT1 and OUT2.

Figure 9. Time Interval Configuration Using an External Clock, Set,

and Clock Inhibit Functions

(Divide–by–2 Configured)

MOTOROLA CMOS LOGIC DATA

MC14536B

9

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