MC26LS30
0 or 3.0 V
Vin
VCC
500 pF
RL VSS
En
450 Ω
S.G.
1.5 V
Vin
tPHZ
(Vin = Hi)
Output
Current
tPLZ
(Vin = Lo)
NOTES:
1. S.G. set to: f p 1.0 MHz; duty cycle = 50%; tr, tf, p 10 ns.
2. Above tests conducted by monitoring output current levels.
0.1 VSS/RL
0.1 VSS/RL
+3.0 V
1.5 V
0V
VSS/RL
tPZH
0.5 VSS/RL
VSS/RL
0.5 VSS/RL
tPZL
Figure 4. Differential Mode Enable Timing
VCC
Vin
CC
Vin
1.5 V
tPDH
450
VEE
S.G.
500 pF
VO
90%
50%
Vout 10%
tr
NOTES:
1. S.G. set to: f p 100 kHz; duty cycle = 50%; tr, tf, p 10 ns.
2. tSK4 = tPDH−tPDL for each driver.
3. tSK5 computed by subtracting the shortest tPDH from the longest tPDH of the 4 drivers within a package.
4. tSK6 computed by subtracting the shortest tPDL from the longest tPDL of the 4 drivers within a package.
+2.5 V
1.5 V
0V
tPDL
90%
50%
10%
tf
Figure 5. Single−Ended Mode Rise/Fall Time and Data Propagation Delay
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