TIMING DIAGRAMS
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
RST
0.2 VDD
tw(RST)
CS
0.2 VDD
SCLK
tLEAD
0.7 VDD
tw(SCLKH)
0.2 VDD
SI
Don't Care
tSI(su)
0.7 VDD
Valid
0.2 VDD
tR
tw(SCLKL)
tSI(hold)
Don't Care
tLAG
tF
Valid
Figure 4. Input Timing Switch Characteristics
ELECTRICAL PERFORMANCE CURVES
VIH
VIL
VIH
VIL
VIH
VIL
VIH
Don't Care
VIL
SCLK
VDD = 5.0 V
33298
Under
Test
SO
CL = 200 pF
VDD = 5.0 V
VPull-Up = 2.5 V
33298
CS
Under
Test
RL = 1.0 kΩ
SO
CL = 20 pF
CL represents the total capacitance of the test fixture and probe.
Figure 5. Valid Data Delay Time and
Valid Time Test Circuit
L ρεπρεσεντσ τηε τοταλ χαπαχιτανχε οφ τηε τεστ φιξτυρε ανδ προβε
Figure 6. Enable and Disable Time Test Circuit
Analog Integrated Circuit Device Data
Freescale Semiconductor
33298
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