MCM69R820C データシートの表示（PDF） - Motorola => Freescale
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MCM69R820C Datasheet PDF : 20 Pages
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Freescale Semiconductor, Inc.
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V ± 5%, 0°C ≤ TA ≤ 70°C, Unless Otherwise Noted)
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 2.5 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . 1 V/ns (20% to 80%)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . 1.25 V
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . 1.25 V
Clock Input Timing Reference Level . . . . . . Differential Cross–Point
Clock Input Pulse Level . . . . . . . . . . . . . . . . . . . . . . . . . 1.8 V to 2.1 V
RθJA Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22°C/W
READ/WRITE CYCLE TIMING
69R738C–4
69R820C–4
Parameter
Symbol Min Max
Cycle Time
Clock High Pulse Width
Clock Low Pulse Width
Clock High to Output Low–Z
Clock High to Output Valid
Clock High to Output Hold
Clock High to Output High–Z
Output Enable Low to Output
Low–Z
tKHKH
4
—
tKHKL 1.5
—
tKLKH 1.5
—
tKHQX1 0.5
—
tKHQV
—
2
tKHQX 0.7
—
tKHQZ
—
2
tGLQX 0.5
—
Output Enable Low to Output
Valid
tGLQV
—
2
Output Enable to Output Hold
Output Enable High to Output
High–Z
tGHQX 0.5
—
tGHQZ
—
2
ZZ High to Sleep Mode
tZZE
—
50
ZZ Low to Recovery
tZZR
200
—
Setup Times:
Address tAVKH 0.5
—
Data In tDVKH
Chip Select tSVKH
Write Enable tWVKH
Hold Times:
Address tKHAX 0.75
—
Data In tKHDX
Chip Select tKHSX
Write Enable tKHWX
NOTES:
1. This parameter is sampled and not 100% tested.
2. Measured at ±200 mV from steady state.
69R738C–4.4
69R820C–4.4
Min Max
4.4
—
1.5
—
1.5
—
1
—
—
2.2
0.7
—
—
2.2
0.5
—
—
2.2
0.5
—
—
2
—
50
200
—
0.5
—
0.75
—
69R738C–5
69R820C–5
Min Max
5
—
2
—
2
—
1
—
—
2.5
1
—
—
2.5
0.5
—
—
2.5
0.5
—
—
2.5
—
50
200
—
0.5
—
1
—
69R738C–6
69R820C–6
Min Max
6
—
2.4
—
2.4
—
1
—
—
3
1
—
—
3
0.5
—
—
3
0.5
—
—
3
—
50
200
—
0.5
—
1
—
Unit Notes
ns
ns
ns
ns
1, 2
ns
ns
1
ns
1, 2
ns
ns
ns
ns
1, 2
ns
ns
ns
ns
DEVICE
UNDER
TEST
VDDQ/2
50 Ω
50 Ω
TIMING LIMITS
The table of timing values shows either a mini-
mum or a maximum limit for each parameter. Input
requirements are specified from the external system
point of view. Thus, address setup time is shown as
a minimum since the system must supply at least
that much time. On the other hand, responses from
the memory are specified from the device point of
view. Thus, the access time is shown as a maximum
since the device never provides data later than that
time.
Figure 1. AC Test Load
MCM69R738C•MCM69R820C For More Information On This Product,
8
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