MCP3901A0I/SS データシートの表示（PDF） - Microchip Technology

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MCP3901A0I/SS

Two-Channel Analog Front End

Microchip Technology 

MCP3901

DR

SCK

SDO

tDODR

1/DRCLK

tDRP

FIGURE 1-3:

H

SCK

SDO

Data Ready Pulse Timing Diagram.

Timing Waveform for tDO

tDO

Timing Waveform for tDIS

CS

VIH

SDO

90%

tDIS

10%

HI-Z

Timing Waveform for MDAT0/1

Modulator Output

OSC1/CLKI

MDAT0/1

tDOMDAT

FIGURE 1-4:

Specific Timing Diagrams.

OSC1

OSC2

CLKEXT PRESCALE<1:0>

OSR<1:0>

Digital Buffer

1

0

1/

1/Prescale

1/4

MCLK

AMCLK

fS ADC

Sampling

Rate

DMCLK

1/OSR

fD ADC

Output

Data Rate

DRCLK

Crystal

Oscillator

Multiplexer

Clock Divider Clock Divider

Clock Divider

FIGURE 1-5:

MCP3901 Clock Detail.

DS22192D-page 8

© 2011 Microchip Technology Inc.

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