ML6652CM データシートの表示（PDF） - Micro Linear Corporation

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ML6652CM

10/100Mbps Ethernet Fiber and Copper Media Converter with Auto-Negotiation

Micro Linear Corporation 

ML6652

STATUS REGISTERS

Status Registers

Register 27 ADDR 11011 (bin) 1B (hex) All bits are Read Only

Bit Name

15 FOFORCELO

Description

This bit set high when the fiber optic input PLL follows the local oscillator

14 FOBADFREQ

This bit set high when there is a large difference between the frequency of the reference

clock and the frequency of the VCO of the fiber optic input PLL. The low frequency

threshold is between 121 and 123MHz, and the high frequency threshold is between 127

and 129MHz. This indicator is disabled when "FSENSEDIS" bit <28.3> is 1 or when the

filter of the PLL is being reset.

13 FEFDETECT

This bit set high when the Far End Fault (FEF) pattern is detected at the fiber optic input

interface

12 TPFORCELO

This bit set high when the twisted pair input PLL follows the local oscillator

11 TPBADFREQ

This bit set high when there is a large difference between the frequency of the reference

clock and the frequency of the VCO of the twisted pair input PLL. The low frequency

threshold is between 121 and 123MHz, and the high frequency threshold is between 127

and 129MHz. This indicator is disabled when "FSENSEDIS" bit <28.3> is 1 or when the

filter of the PLL is being reset.

10

NOSEED

This bit set high when the descrambler is enabled and the seed is not updated for 1.3ms

to 2ms. This bit set low when the seed is updated. The high value is latched until it’s

read. Default is 0

9 TPLINKSTATUS

This bit set high when the twisted pair link is up. This bit is latched low until read. It only

applies to NON-TRANSPARENT Mode. It is always low in TRANSPARENT Mode

8

ANCOMPL

Auto-Negotiation Complete. This bit set high indicates that the Auto-Negotiation process

on the twisted pair link is completed. It only applies to NON-TRANSPARENT Mode. It is

always low in TRANSPARENT Mode

7

TPIN100

This bit set high indicates that 100Mbps signal is being detected at the twisted pair input

interface

6

TPIN10

This bit set high indicates that 10Mbps signal is being detected at the twisted pair input

interface

5

DATACTOF

This bit set high indicates that a data packet has been detected at the twisted pair input.

This bit is latched high until it’s read. This bit is always low if both TPIN10 and TPIN100

are low

4

FLP

This bit set high, when FLP Bursts are detected at the twisted pair input interface. It is

also set high when FLNP Bursts are detected at the twisted pair interface when PECL

mode is selected for it

3

FOIN100

This bit set high when 100BASE-FX or 100BASE-SX signal is being detected at the fiber

optic input interface

2

FOIN10

This bit set high when 10BASE-FL signal is being detected at the fiber optic input

interface

1

DATAFTOC

This bit set high when a data packet has been detected at the fiber optic input. This bit is

latched high until it’s read. This bit is always low if both FOIN10 and FOIN100 are off

0

FLNP

This bit set high when FLNP Bursts are detected at the fiber optic input interface

23

January 2004

Final Datasheet

DS6652-F-02

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