MPC9456
Freescale Semiconductor, Inc.
PCLK
Bank A
QA0
CLK
0
25k
QA1
PCLK
CLK ÷ 2
1
QA2
25k VCC/2
Bank B
QB0
0
QB1
1
QB2
FSELA
25k
FSELB
25k
FSELC
25k
MR/OE
25k
QC0
Bank C
0
QC1
1
QC2
QC3
Figure 1. MPC9456 Logic Diagram
VCCA
QA2
GND
QA1
VCCA
QA0
GND
MR/OE
24 23 22 21 20 19 18 17
25
16
26
15
27
14
28
13
MPC9456
29
12
30
11
31
10
32
9
12345678
VCCB is internally connected to VCC
QC3
GND
QC2
VCCC
QC1
GND
QC0
VCCC
MOTOROLA
Figure 2. Pinout: 32–Lead Package Pinout (Top View)
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TIMING SOLUTIONS