MSM7652 データシートの表示（PDF） - Oki Electric Industry

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MSM7652

NTSC/PAL Digital Video Encoder

Oki Electric Industry 

¡ Semiconductor

MSM7652

CLOCK TIMING2 (8bit Y/8bit CbCr input)

Input Data Timing

Input data and sync signals are fed into the encoder at the rising edge of CLKX2.

Input data is handled as valid pixel data when tSTART passes after the falling edge of HSYNC_L.

Chrominance signal of input data at this time is regarded as Cb.

CLKX2

tSTART

ACTIVE VIDEO LINE

tACT

HSYNC_L

YD, CD,

OLR, OLB,

OLG,OLC

BLANK_L

ts1

don't care

th1

VALID DATA

don't care

Video data input timing

Input data is recognized as valid pixel data when input signal BLANK_L is "H" in the tACT period.

When BLANK_L is "H" during the blanking period, however, input data is not output as valid

pixel data since processing to maintain blanking period is internally in-progress.

The values of tSTART differ slightly between in master mode and in slave mode. The values of

tSTART are as follows.

In YCbCr format input mode, the values of tSTART are the same, in 8 bit (Y) + 8 bit (CbCr) mode

or in 8 bit (YCbCr) mode.

In master mode

Operation mode

ITU 601 NTSC

ITU 601 PAL

tSTA – tS1 = tSTART

tSTA(Ts)

250

280

In slave mode

Operation mode

ITU 601 NTSC

ITU 601 PAL

tSTA(Ts)

260

290

15

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