MSM7662 データシートの表示（PDF） - Oki Electric Industry

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MSM7662

NTSC/PAL Digital Video Decoder

Oki Electric Industry 

¡ Semiconductor

INPUT AND OUTPUT TIMING

Clock and Output Timing

CLKSEL: H

tCLKX1

CLKX2

tCXD21

CLKX2O

CLKXO

Y[7:0], C[7:0]

B[7:0]

HVALID, VVALID,

ODD

HSYNC_L,

VSYNC_L

STATUS[3:1]

M[7:4]

tCXD11

tOD11

tOD2X11

tODX11

tOD12

tOD2X12

tODX12

tOD13

tOD2X13

tODX13

Data Delay (when a standard signal is input)

PEDL7662-02

MSM7662

CLKSEL: L

tCLKX2

tCXD22

tCXD21

tOD21

tOD2X21

tODX21

tOD22

tOD2X22

tODX22

tOD23

tOD2X23

tODX23

Analog Video In

Decoder output

Blank delay

Data delay

Blank

Active Data

Video Mode

NTSC

NTSC

PAL

PAL

NTSC, PAL

NTSC, PAL

Input Signal

Composite

Composite

Composite

Composite

S-Video

S-Video

T = 1 pixel rate, a = absorption difference

FIFO/FM Mode Amount of Delay

FIFO-1

1H + 358T ±a

FM

1H + 358T

FIFO-1

1H + 358T ±a

FM

1H + 358T

FIFO-1

358T ±a

FM

358T

The data delay is equal to the blank delay. 1H depends on the sampling mode.

The numeric value (T value) may be changed according to a signal state.

Since the output period is fixed during FIFO mode, the amount of delay is changed.

If Y/C separation is performed using TRAP filter during PAL mode, 1H is not added.

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