MSM7662 データシートの表示（PDF） - Oki Electric Industry
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MSM7662 Datasheet PDF : 62 Pages
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¡ Semiconductor
PEDL7662-02
MSM7662
TIMING DESCRIPTION
Vertical Synchronizing Signal
The vertical synchronizing signal timing is as follows. The default output is as shown below, but
the internal processing of the synchronizing signal is performed before 1H.
CVBS
HVALID
HSYNC_L
VSYNC_L
CSYNC_L
VVALID
ODD
CVBS
HVALID
HSYNC_L
VSYNC_L
CSYNC_L
VVALID
ODD
524 525 1 2 3 4 5 6 7 8 9
21 22
262 263 264 265 266 267 268 269 270 271
283 284 285
Vertical Synchronizing Signal (60 Hz)
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