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MT28F322P3 データシートの表示(PDF) - Micron Technology

部品番号
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MT28F322P3
Micron
Micron Technology 
MT28F322P3 Datasheet PDF : 36 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
PRELIMINARY
2 MEG x 16
ASYNC/PAGE FLASH MEMORY
BALL DESCRIPTIONS
48-BALL FBGA
NUMBERS
D8, C8, B8, C7,
A8, B7, C6, A7,
A3, C3, B2, A2,
C2, A1, B1, C1,
D1, B6, B5, A6,
C5
D7
SYMBOL
A0–A20
CE#
TYPE
Input
Input
F8
OE#
Input
B3
WE#
Input
B4
RST#
Input
A5
WP#
Input
A4
VPP
Input
E7, F7, D5, E5,
F4, D3, E3, F2,
D6, E6, F6, D4,
E4, F3, D2, E2
E8, F1
F5
DQ0–DQ15
VSS
VCC
Input/
Output
Supply
Supply
E1
VCCQ
Supply
C4
NC
DESCRIPTION
Address Inputs: Inputs for the address during READ and WRITE
operations. Addresses are internally latched during READ and WRITE
cycles.
Chip Enable: Activates the device when LOW. When CE# is HIGH, the
device is disabled and goes into standby power mode.
Output Enable: Enables the output buffer when LOW. When OE# is
HIGH, the output buffers are disabled.
Write Enable: Determines if a given cycle is a WRITE cycle. If WE# is
LOW, the cycle is either a WRITE to the command state machine
(CSM) or to the memory array.
Reset: When RST# is a logic LOW, the device is in reset mode, which
drives the outputs to High-Z and resets the write state machine
(WSM). When RST# is at logic HIGH, the device is in standard
operation. When RST# transitions from logic LOW to logic HIGH, the
device resets all blocks to locked and defaults to the read array
mode.
Write Protect: Controls the lock down function of the flexible locking
feature.
Program/Erase Enable: [1.8V–3.3V] Operates as input at logic levels to
control complete device protection. Provides factory programming
compatibility when driven to 11.4V–12.6V.
Data Inputs/Outputs: Input array data on the second CE# and WE#
cycle during PROGRAM command. Input commands to the
command user interface when CE# and WE# are active. DQ0–DQ15
output data when CE# and OE# are active.
Do not float any ground ball.
Device Power Supply: [2.7V–3.3V] Supplies power for device
operation.
I/O Power Supply: [2.2V–3.3V] Supplies power for input/output
buffers.
Internally not connected.
2 Meg x 16 Async/Page Flash Memory
MT28F322P3FJ_3.p65 – Rev. 3, Pub. 7/02
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.

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