CY7C187-20PC データシートの表示（PDF） - Cypress Semiconductor
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CY7C187-20PC Datasheet PDF : 9 Pages
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CY7C187
AC Test Loads and Waveforms
5V
OUTPUT
R1 329 Ω
(480Ω MIL)
5V
OUTPUT
R1 329 Ω
(480 Ω MIL)
30 pF
INCLUDING
JIG AND
SCOPE
R2 202 Ω
(R1 255 Ω MIL)
5 pF
INCLUDING
JIG AND
(a)
SCOPE (b)
R2 202 Ω
(R1 255 Ω MIL)
C187–4
3.0V
10%
GND
≤ 5 ns
ALL INPUT PULSES
90%
90%
10%
≤ 5 ns
C187–5
Equivalent to: THÉVENIN EQUIVALENT
OUTPUT
167Ω
Military
1.73V
OUTPUT
125Ω
1.90V
Commercial
Switching Characteristics Over the Operating Range[6]
7C187-15
7C187-20
Parameter
Description
Min. Max. Min. Max.
Unit
READ CYCLE
tRC
tAA
tOHA
tACE
tLZCE
tHZCE
tPU
tPD
WRITE CYCLE[9]
Read Cycle Time
Address to Data Valid
Output Hold from Address Change
CE LOW to Data Valid
CE LOW to Low Z[7]
CE HIGH to High Z[7, 8]
CE LOW to Power Up
CE HIGH to Power Down
15
20
ns
15
20
ns
3
5
ns
15
20
ns
3
5
ns
8
8
ns
0
0
ns
15
20
ns
tWC
Write Cycle Time
15
20
ns
tSCE
CE LOW to Write End
12
15
ns
tAW
Address Set-Up to Write End
12
15
ns
tHA
Address Hold from Write End
0
0
ns
tSA
Address Set-Up to Write Start
0
0
ns
tPWE
WE Pulse Width
12
15
ns
tSD
Data Set-Up to Write End
10
10
ns
tHD
Data Hold from Write End
0
0
ns
tLZWE
tHZWE
WE HIGH to Low Z
WE LOW to High Z[8]
5
5
ns
7
7
ns
Notes:
6. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE for any given device.
8. tHZCE and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Document #: 38-05044 Rev. **
Page 3 of 9
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