MT48LC16M4A2 データシートの表示（PDF） - Micron Technology

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MT48LC16M4A2

64Mb: x4, x8, x16 SDRAM

Micron Technology 

64Mb: x4, x8, x16

SDRAM

READ – WITHOUT AUTO PRECHARGE 1

T0

CLK

tCKS tCKH

CKE

tCMS tCMH

COMMAND

ACTIVE

DQM /

DQML, DQMH

A0-A9, A11

tAS tAH

ROW

A10

BA0, BA1

tAS tAH

ROW

tAS tAH

BANK

T1

T2

T3

tCK

tCL

tCH

NOP

READ

NOP

tCMS tCMH

COLUMN m2

DISABLE AUTO PRECHARGE

BANK

DQ

tRCD

tRAS

tRC

tAC

tLZ

CAS Latency

T4

NOP

tAC

tOH

DOUT m

T5

T6

T7

NOP

PRECHARGE

NOP

ALL BANKS

SINGLE BANKS

tAC

tOH

DOUT m+1

BANK(S)

tAC

tOH

DOUT m+2

tRP

tOH

DOUT m+3

tHZ

T8

ACTIVE

ROW

ROW

BANK

TIMING PARAMETERS

-6

SYMBOL*

tAC(3)

tAC(2)

tAH

tAS

tCH

tCL

tCK(3)

tCK(2)

tCKH

tCKS

MIN

1

1.5

2.5

2.5

6

–

1

1.5

MAX

5.5

–

-7E

MIN MAX

5.4

5.4

0.8

1.5

2.5

2.5

7

7.5

0.8

1.5

-75

MIN MAX

5.4

6

0.8

1.5

2.5

2.5

7.5

10

0.8

1.5

-8E

MIN MAX UNITS

6 ns

6 ns

1

ns

2

ns

3

ns

3

ns

8

ns

10

ns

1

ns

2

ns

*CAS latency indicated in parentheses.

DON’T CARE

UNDEFINED

-6

-7E

-75

-8E

SYMBOL* MIN MAX MIN MAX MIN MAX MIN MAX UNITS

tCMH

1

0.8

0.8

1

ns

tCMS

1.5

1.5

1.5

2

ns

tHZ(3)

5.5

5.4

5.4

6 ns

tHZ(2)

–

5.4

6

6 ns

tLZ

1

1

1

1

ns

tOH

2

3

3

3

ns

tRAS

42 120,000 37 120,000 44 120,000 50 120,000 ns

tRC

60

60

66

70

ns

tRCD

18

15

20

20

ns

tRP

18

15

20

20

ns

NOTE:

1. For this example, the burst length = 4, the CAS latency = 2, and the READ burst is followed by a “manual” PRECHARGE.

2. x16: A8, A9 and A11 = “Don’t Care”

x8: A9 and A11 = “Don’t Care”

x4: A11 = “Don’t Care”

64Mb: x4, x8, x16 SDRAM

64MSDRAM_F.p65 – Rev. F; Pub. 1/03

41

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2003, Micron Technology, Inc.

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