NCP1231P133G データシートの表示（PDF） - ON Semiconductor

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NCP1231P133G

Low−Standby Power High Performance PWM Controller

ON Semiconductor 

NCP1231

Feedback

The feedback pin has been designed to be connected

directly to the open−collector output of an optocoupler. The

pin is pulled−up through a 20 kW resistor to the internal Vdd

supply (6.5 volts nominal). The feedback input signal is

divided down, by a factor of three, and connected to the

negative (−) input of the PWM comparator. The positive (+)

input to the PWM comparator is the current sense signal

(Figure 31).

The NCP1231 is a peak current mode controller, where

the feedback signal is proportional to the output power. At

the beginning of the cycle, the power switch is turns−on and

the current begins to increase in the primary of the

transformer, when the peak current crosses the feedback

voltage level, the PWM comparators switches from a logic

level low, to a logic level high, resetting the PWM latching

Flip−Flop, turning off the power switch until the next

oscillator clock cycle begins.

Vdd

20k

FB

55k

2

− PWM

10 V

25k

+

2.3 Vpp

Ramp

18 k

3

LEB

where:

Ipk

+

0.75

Rs @ 3

Ipk @ Rs + 1V

Ǹ Ipk +

2 @ Pin

Lp @ f

where:

Pin = is the power level where the NCP1231 will go into

the skip mode

Lp = Primary inductance

f = NCP1231 controller frequency

Pin

+

Lp

@

f@

2

Ipk2

Pin

+

Pout

Eff

where:

Eff = the power supply efficiency

Rout

+

Eout2

Pout

Vskip

/ Vstby−out

+

1.25 V

+

−

Fault

S is rising edge triggered

R is falling edge triggered

100 ms

S

R

Vdd

Figure 31.

The feedback pin input is clamped to a nominal 10 volt for

ESD protection.

Skip Mode

The feedback input is connected in parallel with the skip

cycle logic (Figure 32). When the feedback voltage drops

below 25% of the maximum peak current (1 V/Rsense) the

IC prevents the current from decreasing any further and

starts to blank the output pulses. This is called the skip cycle

mode. While the controller is in the burst mode the power

transfer now depends upon the duty cycle of the pulse burst

width which reduces the average input power demand.

Vc + Ipk @ Rs @ 3

where:

Vc = control voltage (Feedback pin input),

Ipk = Peak primary current,

Rs = Current sense resistor,

3 = Feedback divider ratio.

SkipLevel + 3V @ 25% + 0.75V

FB

−

Vskip

+

+

0.75 V

CS Cmp

PFC_VCC

Latch

Reset

Figure 32.

During the skip mode the PFC_Vcc signal (pin 1) is

asserted into a high impedance state when a light load

condition is detected and confirmed, Figure 33 shows

typical waveforms. The first section of the waveform shows

a normal startup condition, where the output voltage is low,

as a result the feedback signal will be high asking the

controller to provide the maximum power to the output. The

second phase is under normal loading, and the output is in

regulation. The third phase is when the output power drops

below the 25% threshold (the feedback voltage drops to 0.75

volts). When this occurs, the 100 mses timer starts, and if the

conditions is still present after the time output period, the

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