NCP1231P133G データシートの表示（PDF） - ON Semiconductor

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NCP1231P133G

Low−Standby Power High Performance PWM Controller

ON Semiconductor 

NCP1231

Thermal Shutdown

Skip

100 msec Timer

2.3 Vpp

PWM Comparator

Ramp FB/3

−

+ Vccreset

3 CS

18 k

LEB

250 ns

10 V

RQ

+

− Latch−Off S

3V

Figure 35.

Short−Circuit Condition

The NCP1231 is different from other controllers which

uses auxiliary windings to detect events on the isolated

secondary output. There maybe some conditions (for

example when the leakage inductance is high) where it can

be extremely difficult to implement short−circuit and

overload protection. This occurs because when the power

switch opens, the leakage inductance superimposes a large

spike on the switch drain voltage. This spike is seen on the

isolated secondary output and on the auxiliary winding.

Because the auxiliary winding and diode form a peak

rectifier, the auxiliary VCC capacitor voltage can be charged

up to the peak value rather than the true plateau which is

proportional to the output level.

To resolve these issues the NCP1231 monitors the 1.0 V

error flag. As soon as the internal 1.0 V error flag is asserted

high, a 100 ms timer starts. If at the end of the 100 ms timeout

period, the error flag is still asserted then the controller

determines that there is a true fault condition and stops the

PWM drive output, refer to Figure 36. When this occurs,

VCC starts to decrease because the power supply is locked

out. When VCC drops below UVLOlow (7.7 V typical), it

enters a latch−off phase where the internal consumption is

reduced down to 30 mA. This reduction in current allows the

VCC capacitor to be charged up through the external startup

resistor, when VCC reaches VCCON (12.6 V), the soft−start

circuit is activated and the controller goes through a normal

startup. If the fault has gone and the error flag is low, the

controller resumes normal operations.

Under transient load conditions, if the error flag is

asserted, the error flag will normally drop prior to the 100 ms

timeout period and the controller continues to operate

normally.

If the 100 msec timer expires while the NCP1231 is in the

Skip Mode, SW1 opens and the PFC_Vcc output will shut

down and will not be activated until the fault goes away and

the power supply resumes normal operations.

While in the Skip Mode, to avoid any thermal runaway it

is desirable for the skip duty cycle to be kept below 20%(the

burst duty−cycle is defined as Tpulse / Tfault).

The latch−off phase can also be initiated, more classically,

when VCC drops below UVLO (7.7 V typical). During this

fault detection method, the controller will not wait for the

100 ms time−out, or the error flag before it goes into the

latch−off phase, operating in the skip mode under these

conditions.

regulation

12.6V

7.7V

Vcc

PWM

Stby stby is left

Short−circuit

Nom

Pout

regulation

100ms

Timer

100ms

5ms

1.0 V SS

Flag

Pin1

PFC

Vcc

100ms

100ms

Stby

confirmed

Figure 36.

http://onsemi.com

15

100ms

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