NLSX5012DMR2G(2010) データシートの表示（PDF） - ON Semiconductor

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NLSX5012DMR2G
(Rev.:2010)

2-Bit 100 Mb/s Configurable Dual-Supply Level Translator

ON Semiconductor 

NLSX5012

+1.8V

+1.8 V System

VL

+3.6V

VL

VCC

NLSX5012

+3.6 V System

I/O VL

I/O1

I/On

GND OE

I/O VL1 I/O VCC1

I/O VLn I/O VCCn

EN GND

I/O1

I/On

GND

P

One−Shot

R1

N

One−Shot

P

One−Shot

R2

N

One−Shot

VCC

I/O VCC

Figure 1. Typical Application Circuit

Figure 2. Simplified Functional Diagram (1 I/O Line)

2.5 V

3.0 V

2.5 V

1.8 V

mC

TX

RX

ANO

VL

VCC

NLSX5012

I/O VL1 I/O VCC1

I/O VL2 I/O VCC2

EN

GND

Peripheral

RX

TX

mC

TX

RX

ANO

VL

VCC

NLSX5012

I/O VL1 I/O VCC1

I/O VL2 I/O VCC2

EN

GND

Peripheral

RX

TX

Figure 3. Application Example for VL < VCC

Figure 4. Application Example for VL > VCC

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