NLSX5012DMR2G(2010) データシートの表示（PDF） - ON Semiconductor

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NLSX5012DMR2G
(Rev.:2010)

2-Bit 100 Mb/s Configurable Dual-Supply Level Translator

ON Semiconductor 

EN

I/O VL1

NLSX5012

VL VCC GND

I/O VCC1

I/O VL2

I/O VCC2

Figure 5. Logic Diagram

VL 1

I/O VL1 2

I/O VL2 3

GND 4

8 VCC

7 I/O VCC1

6 I/O VCC2

5 EN

UDFN8

(Top View)

VL 1

I/O VL1 2

I/O VL2 3

GND 4

8 VCC

7 I/O VCC1

6 I/O VCC2

5 EN

SOIC−8

(Top View)

VL

I/O VL1

I/O VL2

GND

Figure 6. Pin Assignments

1

8

2

7

3

6

4

5

Micro8

(Top View)

VCC

I/O VCC1

I/O VCC2

EN

PIN ASSIGNMENT

Pins

Description

VCC

VL

GND

VCC Input Voltage

VL Input Voltage

Ground

EN

Output Enable

I/O VCCn

I/O VLn

I/O Port, Referenced to VCC

I/O Port, Referenced to VL

FUNCTION TABLE

EN

L

H

Operating Mode

Hi−Z

I/O Buses Connected

http://onsemi.com

3

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