NLSX5012 データシートの表示（PDF） - ON Semiconductor

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NLSX5012

2-Bit 100 Mb/s Configurable Dual-Supply Level Translator

ON Semiconductor 

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

SCALE 2:1

Micro8

CASE 846A−02

ISSUE K

DATE 16 JUL 2020

GENERIC

MARKING DIAGRAM*

8

XXXX

AYWG

G

1

XXXX

A

Y

W

G

= Specific Device Code

= Assembly Location

= Year

= Work Week

= Pb−Free Package

(Note: Microdot may be in either location)

*This information is generic. Please refer to

device data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “G”, may

or may not be present. Some products may

not follow the Generic Marking.

STYLE 1:

PIN 1. SOURCE

2. SOURCE

3. SOURCE

4. GATE

5. DRAIN

6. DRAIN

7. DRAIN

8. DRAIN

STYLE 2:

PIN 1. SOURCE 1

2. GATE 1

3. SOURCE 2

4. GATE 2

5. DRAIN 2

6. DRAIN 2

7. DRAIN 1

8. DRAIN 1

STYLE 3:

PIN 1. N-SOURCE

2. N-GATE

3. P-SOURCE

4. P-GATE

5. P-DRAIN

6. P-DRAIN

7. N-DRAIN

8. N-DRAIN

DOCUMENT NUMBER: 98ASB14087C

DESCRIPTION: MICRO8

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 1 OF 1

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