NTE797 データシートの表示（PDF） - NTE Electronics

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NTE797

Integrated Circuit TV Chroma Processor

NTE Electronics 

Electrical Characteristics: (TA = +25°C, chroma control at maximum position for all character-

istics test except for chroma output test. For this test, control should be set at minimum position.)

Characteristic

Test

Chroma

Measurement Switch Pos. Input

& Symbol

S1

S2

TP1 Min Typ Max Unit

Static Characteristics

Voltage Regulator

Supply Current

V12

2

2

0

10.1 11.2 12.1

V

Dynamic Characteristics (Note 2)

Pull−In Range (Note 3)

Oscillator Output

100% Chroma Output

Overload Detector

Minimum Chroma Output

200% Chroma Output

20% Chroma Output

Kill Level

V8

V8

V15

V15

V15

V15

V15

VTP1

Note 3

2

0.5Vp−p ±250 −

−

Hz

2

2

0

0.6 1.0 −

Vp−p

1

2

0.5Vp−p 1.4 2.7 −

Vp−p

1

1

0.5Vp−p 0.4 − 0.7

Vp−p

1

2

0.5Vp−p −

− 20

mVp−p

1

2

1Vp−p 70 100 140 % of 100%

1

2

0.1Vp−p 40

− 105 reading

1

2

vary

5

− 60

mVp−p

Note 2. Except for pull−in range testing, tune oscillator trimmer capacitor for free−running frequency

of 3.579545 MHz ± 10Hz.

Note 3. Set Switch 1 to Position 2, detune oscillator ±250Hz, set Switch to Position 1, and check for

oscillator pull−in.

Circuit Description:

The chroma input is applied to Pin1 through the desired band−shaping network. A 2,450−ohm resis-

tor should be placed in series with Pin1 to minimize oscillator pickup in the first chroma amplifier. This

amplifier supplies signals to the second chroma amplifier and to the ACC and AFPC detectors. The

first chroma amplifier is gain−controlled by the ACC amplifier. A horizontal keying pulse is applied

to Pin9. This pulse must be present to ensure proper operation of the oscillator circuit. The subcarrier

burst is sampled during the keying interval in the AFPC detector. The error voltage, produced at Pin2

and proportional to the burst phase, is compared to the quiescent bias voltage at Pin3 by the sample−

and−hold circuitry. This “compared” voltage controls the phase−shifting network in the phase−locked

loop. The operation of the AFPC loop is independent of any external adjustments or voltages except

for an initial capacitor adjustment to set the free−running frequency. The regenerated oscillator signal

at Pin8 is applied internally to the AFPC and ACC detectors through +45 − and −45 −degree phase−

shifter networks to establish the proper phase relationship for these detectors. The ACC detectors,

which also samples the burst during the keying interval, produces a correction voltage proportional

to the burst amplitude. The correction voltage is compared to the quiescent bias level using sample−

and−hold circuitry similar to that used in the AFPC portion of the circuit. The “compared” voltage is

applied internally to the ACC amplifier and killer amplifier. Because the amplifier gains and killer thre-

hold are determined by the ratios of the internal resistors, these functions are independent of external

voltages or controls.

The attenuated chroma signal is fed to the second chroma amplifier, where the burst is removed by

keyer action. The killer amplifier, the chroma gain control, and the overload detector control the action

of the second chroma amplifier, whose gain is proportional to the DC voltage at Pin16. The overload

detector (Pin13) receives a sample of the chroma output (Pin15) and detects the peak of the signal.

The detected voltage is stored in an external capacitor connected to Pin16. This stored voltage on

Pin16 affects the gain of the second chroma in the same manner as the chroma gain control.

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