STE100P(2000) データシートの表示（PDF） - STMicroelectronics
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STE100P Datasheet PDF : 29 Pages
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STE100P
Table 4. Register Descriptions
Bit #
Name
Descriptions
Default Val RW Type
10
ISOEN 0 – Normal operation.
0
R/W
1 – Isolate PHY from MII.
Setting this control bit isolates the STE100P from the MII, with
the exception of the serial management inter-face. When this
bit is asserted, the STE100Pdoes not respond to TXD[3:0],
TX-EN, and TX-ER inputs, and it presents a high impedance
on its TX-CLK, RX-CLK, RX-DV, RX-ER, D[3:0], COL, and
CRS outputs. This bit is initialized to 0 unless the configuration
pins for the PHY address are set to 00000h during power-up
or reset.
9
RSAN Re-Start Auto-Negotiation process control.
0
R/W
1: Auto-Negotiation process will be re-started. This bit will be
cleared by STE100P itself after the Auto-negotiation
restarted.
8
DPSEL Full/Half duplex mode select.
0
R/W
1: full duplex mode is selected. This bit will be ignored if Auto-
Negotiation is enabled (bit 12 of PR0 = 1).
7
COLEN Collision test control.
0
R/W
1: collision test is enabled. 0: normal operation
This bit, when set, causes the COL signal to be asserted as a
result of the assertion of TX _EN within 512 BT. De-assertion
of TX_EN will cause the COL signal to be de-asserted within
4BT.
6~0
---
Reserved
0
RO
R/W = Read/Write able. RO = Read Only.
PR1- XSR, XCVR Status Register. All the bits of this register are read only.
15
T4
100BASE-T4 ability.
Always 0, since STE100P has no T4 ability.
0
RO
14
TXFD 100BASE-TX full duplex ability.
1
RO
Always 1, since STE100P has the 100BASE-TX full duplex ability.
13
TXHD 100BASE-TX half duplex ability.
1
RO
Always 1, since STE100P has the 100BASE-TX half duplex ability.
12
10FD 10BASE-T full duplex ability.
1
RO
Always 1, since STE100P has 10Base-T full duplex ability.
11
10HD 10BASE-T half duplex ability.
1
RO
Always 1, since STE100P has 10Base-T half duplex ability.
10~7
---
Reserved
0
RO
6
MFPS MF Preamble Suppression
1
RO
1 =Accepts management frames with pre-amble suppressed.
0 = Will not accept management frames with preamble
suppressed. The value of this bit is controlled by bit 1 of
PR20. Its default of 1 indicates that the SFEPHY1 accepts
management frame without preamble. A minimum of 32
preamble bits are required following power-on or hardware
reset. One IDLE bit is required between any two
management transactions as per IEEE 802.3u
specification.
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